Effective January 1st 2022, ICE Enterprises will increase all product prices by 20%. Market forces, both rising component cost and increasing material lead time, are requiring the first price adjustment in company history. This price increase will allow ICE Enterprises to continue to design and manufacture quality electronic hardware as has been the case for over two decades. ICE Enterprises will honor all current price quotes and accept orders at existing pricing through the end of December 2021.

Packet-Based Architecture

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Packet-based Hardware

  • Seven of the 20+ I/O Modules in production are packet-based.
  • These include FPDP, FPQC, GXD, UDP, SONET, and SONET2.
  • Systems in the field currently capturing 80Mby/sec to disk from SONET and UDP modules.
  • PIC4X and PIC5 have packet-based 800Mby/sec hyper-transport links to processor module sites.
  • The DTDM can wide band resample, tune from 32 to 3000 channels, and demodulate all tuner outputs.
  • On processing modules, each DSP library call (TFD,FFT,DEMOD) is a packet.
  • Tuner chips run at 101MHz. Input FIFO handles oversampling and/or burst data (graychip time-outs)

Packet-based Software

  • Packets in NeXtMidas I/O libraries are handled by a packet handler interface
  • Handlers for ICE, RMIF, and SDDS packet types have been implemented in the ICE tree.
  • X-Midas 380 also supports packets
  • SOURCEPIC/PACKET creates ICE packets for ELCCP processor and others
  • PICFUNC allows packing/unpacking multiple channels with optional strip of packet headers
  • COGS uses separate file of packet headers to index into single packet data file.
  • Archiving to one large packetized file is more efficient that many small files

ICE Packets

  • Header is fixed 64 bytes starting with a 4-byte key.
  • Data size is contained in the header, but is usually fixed at a nominal transfer length.
  • Midas file is type=1000 format=any with PACKET=ICE keyword in main header.
  • ICE packets have 2 double precision time fields, and one double precision sample offset
  • Allows late determination of sample delta, (need this option in X-Midas packets)

SDDS Packets

  • Header is fixed 56 bytes with no key. Data is 1024 bytes. See SDDSPacket.doc
  • Midas file is type 1000, format=SB|SI with PACKET=SDDS keyword in main header.
  • Theoretical max data throughput is 111Mby/sec. Raw 125Mby/sec less overhead (gap=1%, ether=5.5%, sdds=5.5%)
  • ICE-UDP Module FPGA code adds 8 bytes in front with 2-byte key, source port and IP address.
  • The resulting 64 byte header includes essential routing/channel info and keeps accesses on cache lines.
  • Gate array code in the PIC4T/MBT4 interprets timecode field and optionally strips off header.
  • Use /TC=SDDS for raw or tuner data just as with SDN, SMS, CPU, IRIGB, etc.
  • Switch routing through: MidasPrompt> PICD SET <MODxx> IPCONN <address>
  • Initial testing using white noise test file from SDDS hardware, played back via NeXtMidas.
  • Screen shots of packet test through UDP module and through E2D module.
  • Testing against actual SDDS hardware at Aerospace on Sept 29 and Oct 3.
  • Supported in ICE316 on PIC4T and MBT4 cards.

Packet Pitfalls

  • No more dual-channel master/slave on same sample, must use timecode for alignment in downstream processing.
  • SDDS timecode precision to 250psec, but may not represent 1ms hack below 60kHz sample rate. (2^16 * 250psec).
  • Software needs to be enhanced to handle packets robustly.