ICE Help MAINHELP

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MAINHELP - Welcome to the HELP facility for the ICE option tree.

Welcome to the HELP facility for the ICE option tree. This file covers overall concepts and library routines. For information about Midas ICE commands, use EXPLAIN.

The following HELP categories are available:

GENERAL  - General (collection of concepts & features)
CARDS    - Brief description of the ICE-DSP cards and I/O Modules
ICELIB   - High level control software for ICE-DSP cards
FLAGS    - Flags for modifying behavior of ICELIB libraries
QUALS    - File qualifiers affecting ICE ramdisk and archive files
KEYS     - Key names for accessing parameters 
DRIVERS  - Low level drivers for ICE-DSP cards
CORES    - Interface definition for ICE FPGA cores
JVCC     - Java Verilog Cross Compiler
ICEOS    - ICE Operating System for srvIce's and devIce's
IOC      - Current IOC code algorithms
SOC      - Current SoC code algorithms
PCI      - Current PCI revision capabilities
GPS      - Current GPS module capabilities
CRCs     - Current CRCs for all non-volatile EEProms
STATUS   - Status interface to ICE products
PACKETS  - Packet formats and capabilities
SRVICE   - Script based ICE application helper
NETWORK  - Network interface configuration helpers
RELEASE  - Release notes for the current version

GENERAL - A brief description of the general features of the ICE family of DSP cards.

Go to full page: ICE_Help_GENERAL

A brief description of the general features of the ICE family of DSP cards.

PERFORMANCE - Cost/Performance benefits
SCALABILITY - Cards, Chassis, and Interconnects
FLEXIBILITY - Programmable Hardware Concepts
TIMECODE - Handling Embedded TimeCode
OVERSAMPLING - Upsampling Techniques for Digital Tuners
RESAMPLING - Resampling Techniques for Digital Tuners
BOT - Bank Of Tuners on Processor Modules
FTT - Fast Tuner Transform Concept of Operation
DMA - DMA Concepts and Channel Allocation
CHAINING - DMA Chaining Concepts
SHARCMEM - SHARC/PPC Memory Allocation
MIDASDSM - Connecting to an STL Digital Switch Matrix
CLOCKING - Clock sources and selection
PLATFORMS - Notes on specific platforms

CARDS - This file contains a brief text description of the ICE-DSP card architecture.

Go to full page: ICE_Help_CARDS

This file contains a brief text description of the ICE-DSP card architecture. Block diagrams are available in HTML formats only.

Main Boards:

PIC1 - PCI (32 bit, 33MHz, 5V) Tuners (HSP50016 x2)
PIC2 - PCI (64/32 bit, 33MHz, 5V) Tuners (HSP50016 x2)
MBT2 - PCI (64/32 bit, 33MHz, 5V) Tuners (GC4014 x6)
MBT3 - PCI (64/32 bit, 33MHz, 5V) Tuners (GC4014 x6)
PIC3T - PCI (64/32 bit, 33MHz, 5V) Tuners (AD6620 x2)
PIC4T - PCI (64/32 bit, 66/33MHz, 3/5V) Tuners (GC4016 x2)
PIC4X - PCI (64/32 bit, 66/33MHz, 3/5V) PM x1
MBT4 - a PIC4X with a DTDM processor module
MBT4X - a PIC4X with a DTDMX processor module
PIC5 - PCI (64/32 bit, 133/100/66/33MHz, 3V) PM x2
PIC6 - PCI Express (8/4/2/1 Lane, Gen 1) PM x2
PIC7 - PCI Express (8/4/2/1 Lane, Gen 1/2) PM x2
SLIC3A - CardBus SlimPIC (32 bit, 33MHz, 3V) Tuners (GC4014 x1) A2D x2
SLIC3D - CardBus SlimPIC (32 bit, 33MHz, 3V) Tuners (GC4014 x1) IOM x1

Processor Modules:

DTDM - Digital Tuner Demodulator Module
DTDMX - Digital Tuner Demodulator Module with larger FPGA
ZPPM - Virtex-5 based FPGA Module with DSP
V5M - Virtex-5 based FPGA Module
V6M - Virtex-6 based FPGA Module

I/O Modules:

A2D - Analog to Digital Converter Module
D2A - Digital to Analog Converter Module
E2D - Differential ECL to Digital Converter Module
D2E - Digital to Differential ECL Converter Module
PE2D - Positive Differential ECL to Digital Converter Module
T2D - Differential TTL to Digital Converter Module
D2T - Digital to Differential TTL Converter Module
LV2D - LowVoltageDifferentialSignaling to Digital Converter Module
D2LV - Digital to LowVoltageDifferentialSignaling Converter Module
GXD - GigaBit Ethernet Interface Module
UDP - GigaBit Ethernet / Protocol Interface Module
SONET - Synchronous Optical Network Interface Module
CXD - Communications Protocol to Digital Converter Module
UXD - User to/from Digital Converter Module
FPDP - Front Panel DataPort I/O Module
FPQC - Front Panel DataPort / QC64 I/O Module
NFXD - NGC Fiber Input/Output I/O Module
CDR2D - Clock Data Recovery Input I/O Module
DR2D - Differential Receiver I/O Module

ICELIB - This library contains routines to communicate with the ICE family

Go to full page: ICE_Help_ICELIB

This library contains routines to communicate with the ICE family of DSP boards. This includes PIC, MBT, and SLIC varieties. All routines return an int status unless otherwise noted (by the last element in the argument list with the same name as the function). Successful status are >= 0. Errors are signaled by a status < 0.

Arguments that are structures or arrays are passed by reference. All others are pass by value, unless otherwise noted.

Fortran wrappers are provided by preceding the routine name with m$ . All arguments to the wrappers are pass by reference.

PIC_DETECT - Query the current system for ICE cards
PIC_OPEN - Open a connection to an ICE-PIC device
PIC_CLOSE - Close a connection to an ICE-PIC device
PIC_RESET - Reset a device or device IO port
PIC_TEST - Run a series of diagnostic tests
PIC_SNIFF - Display contents of the device PCI/Processor registers
PIC_READ - Read from a PCI or Processor address
PIC_WRITE - Write to a PCI or Processor address
PIC_WRITEM - Write to a PCI or Processor address with a mask
PIC_RFIFO - Read a block of data from the PCI FIFO
PIC_WFIFO - Write a block of data to the PCI FIFO
PIC_RPM - Reads internal address space of a port/processor module
PIC_WPM - Writes internal address space of a port/processor module
PIC_SEND - Send a packet to a port/processor module
PIC_RECV - Receives a packet from a port/processor module
PIC_SENDRECV - Send a packet to a port/processor module and receive response with timeout
PIC_MSG - Send a PKT_ACMD to a Port/Processor Module with optional response and timeout
PIC_IOPORT - Set up an I/O Port for DMA transfer
PIC_TUNER_FREQ - Returns the nearest supported down conversion freq
PIC_TUNER_DEC - Returns the nearest supported decimation
PIC_TUNER_OVSR - Sets the inputs over-sampling ratio (zero insertion)
PIC_FILE - Deprecated use PIC_MAPFILE
PIC_MAPFILE - Prepares a Midas file/buffer for DMA transfers
PIC_MAP - Deprecated, use PIC_MAPMEM
PIC_MAPMEM - Handles allocating/mapping a buffer for DMA transfers
PIC_DMASETUP - Sets up HOST DMA handler
PIC_DMA - Deprecated, use PIC_DMASETUP
PIC_DMAFUNC - Starts, Stops, Polls, or Waits on a DMA transfer
PIC_DMASTAT - Returns the current DMA index, cycle, and status
PIC_DMAXFER - Transfers next available data to/from the host circular buffer
PIC_DMAXPTR - Returns pointer to buffer with the next available DMA data
PIC_DMACHAIN - Set up a DMA chain table entry
PIC_LOADFILE - Loads code from file onto SHARC, PPC, IOC, etc.
PIC_LOADSHARC - Deprecated, use PIC_LOADFILE
PIC_LOADPPC - Deprecated, use PIC_LOADFILE
PIC_LOADIOC - Deprecated, use PIC_LOADFILE
PIC_LOADMOD - Deprecated, use PIC_LOADFILE
PIC_LOADFC - Loads filter coefficients (FC's) from memory buffer onto tuner chip
PIC_TIMER - Deprecated, use PIC_SETKEY with KEY_ICLK 
PIC_NVRAM - Reads/Writes/Converts NVRAM code for PCI-IF chip
PIC_TC - Returns the timecode for a given sample
PIC_TIMECODE - Deprecated, use PIC_TC
PIC_GETINTFLAG - Gets an integer valued flag from the configuration string
PIC_GETDBLFLAG - Gets an double valued flag from the configuration string
PIC_STR2IP - Translates string name into a binary IP address

Single properties should be accessed through the SET/GET KEY routines:

PIC_NAME2KEY - Translates string name into a key ID
PIC_SETKEY - Sets a parameter by key/value pair
PIC_SETKEYL - Sets a 4 byte integer parameter by key/value pair
PIC_SETKEYD - Sets a double parameter by key/value pair
PIC_GETKEY - Gets a parameter by key/value pair
PIC_GETKEYL - Gets a 4-byte integer parameter by key/value pair
PIC_GETKEYD - Gets a double parameter by key/value pair
PIC_GETKEYV - Returns whether the specified key is valid for this port

Valid Keys Include: RATE,FREQ,DEC,GAIN,OVSR,FRAME,CHAIN,MOD,IOC,APP,IPADDR See PIC HELP KEYS for a full list of keyed parameters.

All routines return a status that is 1 for success and -1 for failure unless otherwise noted.

All routines have a FORTRAN callable wrapper. The wrapper name is formed by prepending an M$ and the arguments are all passed by reference. Both C and FORTRAN routines are lowercase.

FLAGS - Flags are typically specified in the config string with either a comma ","

Go to full page: ICE_Help_FLAGS

Flags are typically specified in the config string with either a comma "," or vertical bar "|" as a separator. They modify the standard behavior of the library routines as noted. The ICE Midas primitives take a FLAGS switch to add flags to the current config string. For instance:

SOURCEPIC/flags=(VHS|MUXCLK=A|MSBI)

NOTE: The flags argument in the ioport() routine are NOT for tuner flags.

The tuner flags must be placed in the config string.  

Clocking:

MUXCLK=S - IOC code allowing choice of 6 on-board clock sources
INTCLK - Internally generate clock for IO modules (same as MUXCLK=I)
CLKI - Invert input clock 
CLKRE - Latch data on Rising Edge of Clock instead of default falling edge
NCCLK - Normally, the 1st clock cycle is used to synchronize the enabling of a
PREFX - This option uses the eXternal or clock pin as a reference for the Programmable Clock 
CCLK=F - Specifies the non-standard value of the CCLK crystal in Hertz.
DEGLITCH - Enables deglitch circuit for MUXCLK inputs
CLKDLY=N - Delays input clock by N nanoseconds for clock/data deskew 
PRETRIG=N - Capture N cycles before trigger
PMTHROTTLE=N - throttles Processor Module output to n Mby/s

Data Routing:

MSBI - Invert the Most Significant Bit
LSBX - Replace the LSB with the data on the eXternal sync pin
LSBP - Replace the LSB with the data on the 1PPS sync pin
SPINV - Invert the input spectrum by multiplying every other sample by -1
BIGEND - Invert the bit packing order on SP data
BIT=N - Which bit for single bit acquisitions (0,1,4, or default=15 the MSB)
MBITS=N - When using a Tuner or Core port, this can be used to specify a non-default data
NBITS=N - When using a tuner with a presampler, MBITS sets the Module bits (Presampler input) 
MGAIN=N - When using a Tuner or Core port, this can be used to specify the gain setting for the 
MFREQ=N - When using a Tuner or Core port, this can be used to specify the freq setting for the 
ALT - Use alternate numbered port as source of data
INP=N - Use input n=1 or input n=2 to feed the port
PORT=PORT - This specifies the default port type and index for the pic_ioport() library.
IPORT=PORT - This specifies a non-default input routing for a CORE or TUNER port
OPORT=PORT - This specifies a non-default output routing for a CORE or TUNER port
DELAYPORT=PORT - Select which ports 1=oddTuners 2=evenTuners or 3=allTuners (fed by port1) to

Triggering:

SGO - Slave acq/playback start to opposite channel acting as master
RGO - Ready acq/playback to start with channel on the same side.
TGO - Use bit0 (or ext SMB if XGO and TGO) to trigger start
GGO - Use bit1 (or ext SMB if XGO and GGO) to gate the input clock
XGO - Applied with TGO, GGO, or SGO to use external sync SMB
XTGO - Shorthand for applying XGO and TGO.
XSTGO - Shorthand for applying XGO, SGO and TGO.
MTGO - Use the Module's external sync SMB to trigger start.
XSOE - Enable external sync SMB output
XSTRM - Enable external sync 50ohm termination (on PIC8+)
XSTP - Use the internal test port on the PIC5 to implement the XGO trigger

Filters:

CFIR=NAME - Load the named file into the tuner Coarse (post CIC or CIC correction) Filter.
RFIR=NAME - Load the named file into the tuner Resampler Filter
PFIR=NAME - Load the named file into the tuner Programmable (post CFIR or final output) Filter.
FFIR=NAME - Load the named file into the special Filter Only Core
LUT=NAME - Load the file named "lut_^name" into the post-tuner LUT-based demod.

Tuners:

CHNS=N - Specify the number of configured tuner channels.
CPC=N - Specify the number of channels per tuner chip
FIRONLY - Bypasses the front end of the FPGA based tuners (PIC5+)
UFILT - Use the user defined programmable (PFIR) filter in tuner chips
UCFIR - Use the user defined coarse (CFIR) filter in tuner chips
URFIR - Use the user defined resampler (RFIR) filter in tuner chips on PIC5 boards
NCFIR - Use the narrow-band CFIR coefficients on Graychips.
PFIR4 - Decimate by 4 instead of 2 in PFIR stage on Graychips.
OVSR=N - Set the tuner oversampling factor to N
AOVSR - Automatically apply oversampling ratio to allow lower tuner decimation.
POVSR - Use Post OVSR input rate as the basis for decimation and frequency parameters.
DSYNC - Turn off tuner NCO dither function 
FSYNC - Synchronize tuner frequency changes
TALT1 - All tuners on INP=1 to make a SLIC3 act like half of a PIC4T
ITDEC - Allow independent tuner decimation for each channel on a GC4016.
ITFMT - Allow independent tuner format (SI|CI) for each channel on a GC4016 chip
ITCPC - Allow independent tuner Channels Per Chip (CPC=1|2|4) for each chip on a DTDM or DTDMX.
RESAMP - Enables digital resampling in the tuner
PRESAMP - Enables digital resampling in a tuner core placed in front of this resource
PRETUNE - Normalized frequency for presampler
PREGAIN - Gain for presampler tuner
PRER2C - Enables digital Real to Complex conversion in the R2C core placed in front of this resource.
NORESMON - Disable the PIC5 tuner resampler M over N circuit in favor of a straight
TCLK=N - Sets the internal clock frequency for the Graychips on DTDM/DTDMX modules
PMWBT - Use WideBandTuner mode on Processor Modules
PMWBTR - Use WideBandTuner with WideBandResampler mode on Processor Modules
FTTM=N - Fast Tuner Transform Mode controls various bank of tuners algorithms.

RF Parameters:

RFFREQ=FREQ - Apply RF frequency in MHz
RFBW=FREQ - Apply RF bandwidth in MHz
RFATTN=DB - Apply RF attenuation in dB
RFGAIN=DB - Apply RF gain in dB
RFOPTS=(LIST) - Specify list of options as RFOPTS=(A|B|C) where current list includes:
A2DOPTS=(LIST) - These are currently only parsed for the A2DM14 through A2DM18 modules.
DCSBN=N - Order of exponential averaging in DCS algorithm

High Speed:

HS - Use HighSpeed DMA link port mode (automatic for module/tuner ports).
DUAL - Use two link ports per module (automatic when xfer rate > 38Mby/sec).
QDRX=PORT - Uses both byte lanes per IO module to transfer data at 2x the rate.
VHS - Use SHARC link ports in 48 bit mode for maximum transfer rates.
MEM=ALL - Specify card circular buffer memory to use ALL available
MEM=EXT - Specify card circular buffer memory to use extended memory
CSIZE=N - Specify card circular buffer memory in 1K byte blocks.
COFFS=N - Specify card circular buffer memory offset in 1K byte blocks.
FRAMEDELAY - Delays output of frame decimated output by one frame
A2DPORTS=N - Number of active ports on an A2Dm18 dual site module:

Debug:

VERBOSE - Print commands/status to screen (for debugging)
NOLOCK - Bypass multi-user locking mechanism (for debugging)
PKTBLK=N - Sets blocking factor for output to emulate 10G switch fabric behavior.
NOCLKM - unknown
TO=N - Timeout value in seconds for DMA_WAIT function
TP=N - Test Port number
TPOE=N - Enable Test Port output on 5+ series cards
PMTPOE=N - Enable Test Port output on processor modules
B32 - Only use lower 32 bits of PCI bus (ES45 hot-swap PCI workaround)
FORCE - Force reload of all programmable devices
MODDEBUG=N - Puts IO Module in Debug mode

Config:

NODE=ADDRESS - Specifies the node name this device is plugged in to
SIDE=INDEX - Select a specific side=1 or side=2 of the card
IOC=SIG - Specify name of IO Controller file to load during a reset
IOM=IOMT_NAME - Specifies the type of IO modules on this card by name
IOMFPGA=SIG - Specify name of an FPGA load file to program the IO module
PM=PMT_NAME - Specifies the type of Processor modules on this card by name
PMI=PMINDEX - Specifies the index of the processor module on this card to use for tuner and core resources
PMFPGA=SIG - Specify name of an FPGA load file to program the processor module
NOPM - Specify that there are no Processor Modules on this PIC4X card
BIDIR - Allows Bi-directional modules to be used as input or output without changing
PRC=SIG - Specify name of PRoCessor load file to use, default is "def"
PPC=SIG - Specify name of PowerPC load file to use on a Processor Module, default is "def" 
IOMWAIT=SEC - Number of seconds to wait after module reload for configuration discovery.
NOLOG - Turn off automatic temperature logging except at card reset.
GPSMODE=MODE - Sets non-standard behavior of the GPS module.
GPSOPTS=(LIST) - Specify list of options as GPSOPTS=(A|B|C) where current list includes:
VRT=(LIST) - This flag configures the VRT transmit/receive core parameters.
FFT=(LIST) - This flag configures the FFT core parameters.
CORE=(LIST) - This flag configures the generic CORE parameters.

TimeCode:

TC=MODE - Set the timecode mode as described in the help on pic_tc.
OKNC - Turn off clock loss detect circuit.
NOTCFILL - Do Not require fill bits prior to barker in SDN and DTL modes
OPPSOFFSET=N - Number of clock cycles offset between the 1PPS signal capture and the data capture.
ATCCALIB=N - Additional timecode calibration in units of post tuner/core samples
LEAPSECDOY=N - This tells the ICE libraries that there will be a mid-year leap second on DayOfYear=n

Network:

IPVLAN=VLAN - Specify the Default Virtual Local Area Network address for this UDP module
IPADDR=IP - Specify the IP address of this UDP module
IPCONN=IP - Specify the IP address of for the UDP module to connect to
IPDISC=IP - Specify the IP address of for the UDP module to disconnect from
IPDEST=IP - Specify the IP address of for the UDP module to send to
PREDELAY=N - This option throws away the first N milliseconds of SDDS data packets that are received after the JOIN.
TGPORTS=N - Number of active Ten Gig Ethernet ports on a TGSXD dual site module:
UOPT - User OPTion -  In SDDS modes, leaves ICE/SDDS headers in stream and disables data reformatting 

Network Debug:

RXICESDDS - The default SDDS mode (Native Mode) for proper tuner|module operation and timecode interpretation.
RXRAWDATA - Bring In Every And All Packets Data/Headers.
RXRAWBURST - Bring In All Packet wout/Tx Response.
RXRAWSDDS - Bring In Only SDDS Packet Header & Data, NO UDP,IP Hdrs.
RXSDDSDATA - Bring In Only SDDS Data, No Headers
RXPKTSDDS - Bring In Data With ICE (8 Byte) & SDDS Headers And SDDS Data Without Need For IIS or IOS Download 
RXALLOWPRYPKT - Allow Acquisition Of SDDS Parity Pkts.
RXALLOWNSPKT - Allow Acquisition Of Non-Standard SDDS Pkts.
RXSTRICTOFF - Allow Multiple MC Joins.
RXNOSEQFILL - Do NOT insert filler for dropped SDDS packets based on sequence checks.
RXTCBSWAP - Swaps bits 0 and 3 in 16 bit SDDS packets to move TimeCodeBit=3 into selectable bit=0.
TXRAWDATA - Send Out Packets With 1080 Bytes Of Data, All From User, SDDS Hdr Not Generated
TXRAWSDDS - Send Out Packets With SDDS Hdr (56 Bytes) Generated By Module, 1024 Bytes From User 
TXVLANOVRIDE - Enable protected VLAN range used to insert a signal into the SDDS network
SDDSLEAK=N - Leaks the SDDS packet data at the nominal rate to prevent tuner starvation at low
NOLINK - Disable link negotiation.

NetIO:

NIO=TYPE - Packet type for network IO (ICE,SDDS,VRT,VRTX)
NIOC=N - Number of channels in this DMA multichannel port
IPADDR#=ADDR - IP Address for one of the four SFP 10G ports on the QSFP (where #=1:4 SFP index)
NIOA#=ADDR - Output IP or Multicast Address of this channel output (# is optional multichannel index)
SID#=SID - Stream ID for Vita49 packet mode (# is optional multichannel index)
SR#=RATE - Override computed Sample Rate in MHz (# is optional multichannel index)

SrvIce:

CARD=N - config string for card N is inserted here
PORT=PORT - port on card to use (ie MODULE1,TUNER2,TBANK21)
RATE=RATE - sample rate in Hertz
BITS=BITS - sample size in bits
LENGTH=LEN - length of circular memory buffer in seconds
DIR=IO - direction of transfer (-1=input 1=output)
XFER=LEN - transfer length in bytes
FUNC=FUNC - argument to pic_dmafunc (-2=continuous, >0=#passes)
FILE=FILENAME - filename to write into or read from

Other:

ADGAINFORCE - Turn off A2Dr13 overdrive tracking algorithm.
ADWARNOFF - Turn off warning when using ADGAINFORCE.
ADGAINTRACK - Allow A2Dr13 gain to track signal up/down.
ADDELAY - Have A2D consume the first 1M samples to cover the gain overdrive adjustment transient.
EMT - Sets the parameters for the Envelope Measure and Track function

QUALS - File qualifiers are typically specified in the AFNAME key of a snapapp table.

Go to full page: ICE_Help_QUALS

File qualifiers are typically specified in the AFNAME key of a snapapp table. They modify the standard behavior of the standard Midas library routines as noted. In the snapapp table they need to be specified in quotes if there are more than one. For example:

AFQUAL="FUNC=ICEMULTI,THROTTLE=200"

or

AFQUAL="RG=IFS"

The qualifiers specific to ICE file are:

FUNC=F - Specialized function for the Ice Archiver class
PKTLEN=N - Packet data length in bytes
THROTTLE=N - Maximum data rate to push to network
MAXLINES=N - Number of seperate streams to write at once.
MAXLINESIZE=N - Length of each stream before starting new stream.

KEYS - This file covers all of the keyed parameters that one can set or get using the

Go to full page: ICE_Help_KEYS

This file covers all of the keyed parameters that one can set or get using the pic_getKey() and pic_setKey() routines. Unless specifically noted, all keys are of type int_4.

From Midas these can be called with

PICDRIVER GET <alias> <key> <label>

and

PICDRIVER SET <alias> <key> <value>

From C, Fortran, or Java code, the include file key name defines are formed by prepending KEY_ to the name of the key.

When an index field is required, it is infered from the /PORT=xxx switch or PORT=xxx flag in the card alias. If the PORT is not specified, the /DMAC=n switch provides the index. For an index that does not relate to a DMA channel, such as the TEMP key, use the negative of the index. This bypasses the DMA channel lookup for a port index.

Many of these functions are also supported as flags in the configuration string or /FLAGS=(string) switch. See PIC HELP FLAGS.

The currently supported keys are:

RATE - Input sample rate in Hz
FREQ - Tuned frequency/nyquist (double)
NFREQ - Return the nearest actual tuned frequency/nyquist available.
DFREQ - Channel spacing for tuner banks frequency/nyquist (double)
DEC - Tuner decimation (or frame decimation 1-1024)
NDEC - Return the nearest actual tuner decimation available
GAIN - Tuner gain in dB (must be set after loading user filter coefficients)
EMT - Envelope Measure and Track
ADLM - A2D Load Monitor of signal at input of A2D
MGAIN - Module gain in dB when module has adjustable gain block (typically analog) 
MFREQ - Module center frequency in Hz when module is able to perform a real-to-complex conversion and shift
OVSR - Tuner over-sampling rate
RATIO - Tuner resampler ratio (resamplerOutputRate/tunerOutputRate) (double)
NRATIO - Return the nearest actual tuner resampler ratio available  (double)
FRAME - Frame size (32 <= 2**N <= 512K) for IOC framed decimation (PIC3 and earlier)
PKTLEN - Packet length for tuner bank frames in bytes 
CHAIN - Set DMA chain pointer to specified index (or address)
ACTIVE - Reports number of active DMA channels on card, -1 if not reset, -2 if locked
DELAY - Delay in some applications (in samples)
TCMODE - TimeCode Mode index (debug)
TCOFF - TimeCode offset in Seconds Of Year for applicable output modules.

RFFREQ - RF Module frequency in MHz (double)
RFBW - RF Module bandwidth in MHz (double)
RFATTN - RF Module attenuation in dB
RFGAIN - RF Module gain in dB
RFOPTS - RF Module options mask (See FLAGS)
RFPWR - RF Module input power measurement in dB

FLGBSET - Set specified bits in the common flags
FLGBCLR - Clear specified bits in the common flags
TFLGBSET - Set specified bits in the tuner flags
TFLGBCLR - Clear specified bits in the tuner flags
FLAG - Returns the FLAG field of the indexed DMA structure.
DRVFLG - Returns the FLAG field of the driver status page

IPVLAN - Set the IP VLAN address of an ethernet module
IPADDR - Set the IP address of an ethernet module
IPCONN - Connect to a particular IP multicast port
IPDISC - Disconnect from a particular IP multicast port
PKTHDR - Return the contents of the last ICE/SDDS packet header.
SEQERR - Return the running count of SDDS sequence gaps
SEQFILL - Return the running count of SDDS sequence gaps filled by I/O processor.

ALG - Active algorithm (by index)
ARGS - Algorithm arguments offset

CLKI - Invert the clock
MSBI - Invert the Most Significant Bit
BIT - Bit# for bit serial acquisition (0,1,4,15)
BITS - Number of bits for acquisition (1,8,16)

CTYPE - Card type (2=PIC2 3=PIC3 4=PIC4 8=MBT2 9=MBT3 12=SLIC3)
PTYPE - Port type (1=SERIAL 2=LINK 3=MODULE 4=TUNER)
PINDEX - Port index 1,2,3,4...
MTYPE - IO module type (-1=A2D 1=D2A -2=E2D 2=D2E etc..
MTYPE1 - IO module#1 type
MTYPE2 - IO module#2 type
PMTYPE - Processor module type (1=DTDM 2=DTDMX etc..
PMTYPE1 - Processor module#1 type
PMTYPE2 - Processor module#2 type
PMINDEX - Processor module index (active selection) 0=PIC 1=PM1 2=PM2
MCHNS - Maximum number of tuner channels on board 0-24
CHNS - Number of usable tuner channels 0-24 (uses CPC setting)
CHAN - Select channel in a tuner bank
CPC - Channels per chip to use 1|2|4 (graychips only)
TCINC - Adjacent tuner channel increment (to next tuner on same side)
IOCTYPE - Type of current IOC load module (i.e
CBUFSZ - Default buffer size on card for specified port
STATUS - Current card DMA, ROUTE, and SYSTEM status
ROUTE - Current FPGA routing register
DETECT - Auto detect the current card configuration where the dmac argument is the device number or -1 for all.

PRCCLK - PRoCessor clock rate
IOCCLK - IO Controller chip clock rate
ICLK - IOC Internal divide clock rate (MUXCLK=I)
PCLK - Programmable clock (MUXCLK=P)
CCLK - Motherboard socketed crystal rate (MUXCLK=C)
MCLK - Measurement of clock rate of the specified clock configuration

PCICLK - PCI clock rate (33|66|100|133) MHz
PCIBUS - PCI bus width (32|64) bits
PCIBW - PCI bus bandwidth in Mby/s (theoretical)
PCIREV - PCI controller chip EPROM rev
DRIVER - ICE driver version running on this machine
VERSION - ICE software version loaded on this card
FPGAREV - ICE FPGA firmware versions loaded on this card
FPGASIG - ICE FPGA firmware signature loaded on this card
RSTIME - get time of last reset 
PFIFO - PCI Side FiFo (debug)
AFIFO - Card/Adon Side FiFo (debug)

IOC - IOC registers
IOCIOM - IOC IO Module control register
IOCALG - IOC algorithm register offset
IOCRAM - IOC RAM register offset

MOD - IO Module register offset

CORE - Processing core register offset.

APP - Application register offset.

TEMP - Get temperature measurements from port.
SYSMON - Get temperature/voltage measurements from port.
TPOE - Test port output enable on series 5+ cards
TPD - Test port data
TPDX - Test port data change
TPSR - Test port status register
JTAGPORT - JTAG cable debug port assignment on series 5+ cards
MPCIO - This register controls the 4-bit multi-purpose chip I/O bus
CUID - get the UID Chip 8-byte value
HWREV - get the ICE Hardware Revision 4-byte value
EVCNT - get the 2 16-bit event counters
RTCLK - gets the 8-byte RealTime Clock value.
GPS - gets the time and position from an ICE-GPS IO Module
DUMP - Dumps debug info to the screen for specific cores and modules.
MGTDUMP - Dumps debug info to the screen for specific GigaBit Transceivers.

DRIVERS - This file covers the general operation and installation of low level drivers

Go to full page: ICE_Help_DRIVERS

This file covers the general operation and installation of low level drivers for the supported Operating Systems.

GENERAL - Overview of driver functions
VMS - VMS ICE-DSP Driver Installation Notes 
OSF - OSF ICE-DSP Driver Installation Notes
LNX - Linux ICE-DSP Driver Installation Notes
SOL - SUN Solaris ICE-DSP Driver Installation Notes
SGI - Silicon Graphics ICE-DSP Driver Installation Notes
WIN - Windows ICE-DSP Driver Installation Notes
MAC - MAC-G3 ICE-DSP Driver Installation Notes

CORES - This file contains a brief description of the current interface for user

Go to full page: ICE_Help_CORES

This file contains a brief description of the current interface for user FPGA cores within the ICE FPGA architecture. An ICE Core is an FPGA module with a set of function registers, two dataflow ports, and a test output port.

The verilog implementation signature looks like this:

module userengine (sclk,srst, scs,saddr, swr,swrbus, srd,srdbus, sack,
ioclk, istat,iena,isel,ibus, ostat,oena,osel,obus, test);

or

module mcengine (sclk,srst, scs,saddr, swr,swrbus, srd,srdbus, sack,
ioclk, istat,iena,isel,ibus, ostat,oena,osel,obus, test);

The MultiCore engines are used to handle channelized functions. They can contain 1-16 single channel cores using a common input stream.

If you have access to the ICE FPGA development tree, the full files are $ICEROOT/code/soc/lib/userengine.v and $ICEROOT/code/soc/lib/mcengine.v.

SETUP - Setting up a core for use in a dataflow
NAMING - Core naming rules
ADDRESSING - Register addressing rules
ROUTING - data routing rules
DMA - DMA Crossbar functionality
TRACER - Embedded FPGA debug trace mechanism

JVCC - Motivation:

Go to full page: ICE_Help_JVCC

Motivation:

The ICE-CORE (Code-Once-Run-Everywhere) framework is intended to simplify algorithm development and deployment by using a single test and development methodology when writing code that runs on different platforms such as CPUs, GPUs, VPUs and FPGAs.

The maintenance of these source files can be reduced in many situations by using the ICE-JVCC cross compiler. We define a new language, JavaVerilog, that has the information necessary to automatically generate the Java, C, and SystemVerilog code for various platforms.

Compiler:

The JVCC cross compiler takes in a Java/Verilog coreName.jv file and generates the source code for each of the different platforms. This includes coreName.java for a JVM, coreName.c for a CPU, and coreName.sv for an FPGA supporting SystemVerilog.

The Java and C versions are self contained and will run on any JVM or CPU.

The SystemVerilog version contains instances of Java objects converted into System Verilog modules that can be compiled into .bit files on Xilinx, Altera or any other FPGA supporting SystemVerilog. In this case, the library calls in the C code initialize the objects, load the initial class variables into the FPGA, and start the data flow to execute the core's processing methods in the hardware device.

Language:

The JavaVerilog language follows Java 1.6 constructs with the following extensions:

Integer data types can specify the number of bits, ex. uint6 for a 6 bit integer. The Verilog syntax for selecting bit ranges of an integer is adopted for ease of use. For example: myint[5:3] refers to bits 3 through 5 of the integer myint. Fixed floating point types fptx and dptx are introduced to support FPGA platforms that do not efficiently support IEEE floating point arithmetic.

Flows:

The current JVCC supports three different processing flows: Stream, Buffer, and Array.

The Stream flow is useful for applications working on a stream of data accessing a window of a few samples at a time which is often the case in signal processing.

The Buffer flow is useful for packet processing where one needs random access to data within defined blocks of a data stream.

The Array flow is useful for implementing fixed vector operations.

The first two flows each have one data input stream and one data output stream. The Ice-Core framework handles getting control information and data to/from the core. Alternate frameworks may use OpenCL to implement these control and data flow functions. The compiled FPGA module behaves as an OpenCL kernel.

Data Types:

The Java language supports primitive data types of byte, short, int, long, float and double. JavaVerilog extends this set to include integers of any bit length and fixed floating point types. When implementing these variables on non-FPGA platforms, they are handled by the larger native primitve type. The supported data types are defined in CoreTypes.lst which is read in by the compiler.

Floating point is currently implemented in the FPGA as fixed floating point. The fptx data type is 32 bits with 16 fractional bits to the right of the point. The dptx data type is 64 bits with 32 fractional bits to the right of the point.

Data Structures:

To define data structures that do not have class methods or constructors, the class must extend the DataTypes class. These classes map into C structs and SystemVerilog packed structures. The structure members will be in the order the variables are encountered in the class. The offset of each variable in a class, including data structures, is tracked by the compiler for initialization, run-time modification and readback.

Cores:

Cores are objects that can be accessed by the external world. They are composed of code that can perform operations on local variables, instantiate other Cores or Components, and call Tasks or Functions. They are accessable through a set of C or Java library calls.

core = new Core(N,M)   : instantiates a Core with max usage parameters
core.set(Name,value)   : sets a runtime parameter
value = core.get(Name) : gets a runtime parameter
core.open()            : prepares for processing loop with current parameters
core.process(isb,osb)  : runs the processing loop for a given Input/Output Streams
core.close()           : finishes processing and release resources

Cores currently have one data input stream, one data output stream and a control interface. The public class variables are accessable from the external interface for monitoring and/or real-time control.

Cores can instantiate other cores, components, and tasks.

Components:

Components are blocks of code that implement functions that may be used by this core or others. Their variables are not readable from the external interface but are initialized by their calling core or component.

Components can instantiate other components and tasks, but not cores.

Functions:

Functions for commonly used C math functions are available as methods in the CoreCommon class that both Cores and Components extend. This gives the JV code a more familiar C style for math functions. The functions are typically implemented as 1st order look-up tables in the FPGA code.

Unless called out in CoreFunctions.lst as a task, all functions complete in a single clock.

Tasks:

Tasks are functions that may take multiple clock cycles in the FPGA version. Some Functions are implemented as Tasks automatically. These decisions are guided by the CoreFunctions.lst configuration file which is read in by the compiler.

Declarations:

Although Java and Verilog support declarations almost anywhere in the code, to keep the C translation ANSI comlpiant, all declarations must be completed before the first operational line of code in each method.

Defines:

All static declarations in the JV code are converted to defines in the C and FPGA code. The class constructors in the open() method are used to build the FPGA module resources. This requires all arguments to the constructor to be static variables that create resources for the worst case at runtime.

There are a few special static variables that are reserved for special use:

FLOW=v   : Type of data flow must be STREAM, BUFFER, or ARRAY
PIPE=n   : Pipe mode for loops: 1=On 0=Off -1=Auto (default=AUTO)
BW=n	   : Bus Width in bits for FPGA data interface
IBW=n	   : Input Bus Width in bits for FPGA data interface (default=BW)
OBW=n	   : Output Bus Width in bits for FPGA data interface (default=BW)
MC=n	   : Master Core mode: 1=Core is comprised of other cores, 0=Normal Core
VERBOSE  : Turn on verbose print statements (vprint) for debugging
AUTOLOCAL : Turn class varialbes into locals in the C process method to help optimizer

FPGA Implementation:

The compiler assumes a synchronous design methodology in the FPGA. The system clock is used to supply all control interfaces as well as read the input stream/buffer and write the output stream/buffer. Most statements will use this clock. A 2x clock is available for special loops.

The coreName.sv file contains three sections: Declarations, Sequencer, and Execution.

The variables in the declarations section are allocated much as they are in C. All other statements are then evaluated for input and output variable sensitivity.

The sequencer section uses the sensitivity list to decide which clock on which to execute each line of code. Loops are unrolled in time by default. When pipelined, many of these lines are executing simultaneously. Each equals sign (or other form of assignment) infers a clock edge. Complex equations can be split into simpler equations of similar complexity and combined on the next line to improve timing.

The execution section implements the assignment statements in a single always block except for unrolled loops that are converted to unique generate-for loops with their own 1x or 2x clock.

Directives:

The compiler can be given directives to tune its behavior. They must be entered as in-line comments and will apply to the entire line.

jvc.pipe	: pipeline this for or while loop - this is the default in Stream mode
jvc.clocksPer=N  : number of clocks per pass through pipelined loop
jvc.unroll=N	: unroll or parallelize a loop N indices at a time
jvc.accum=N	: calls out variables for an accumulator unrolled by N 
jvc.clk2x	: use the 2x clock for this loop
jvc.ROM	: implement array as Read Only Memmory, compiler handles initialization
jvc.passive	: this object is passed between two components and needs special handling

Compiler directives are case insensitive.

ICEOS - Motivation:

Go to full page: ICE_Help_ICEOS

Motivation:

The ICE-PAC and ICE-SuperPAC use an Intel CPU in the Q-Seven form factor for control and configuration. While these are capable processors, they only draw 5-8 watts and are not high end servers. The internal M.2 drive holds 128GBy and will max out at about 120MBy/s. The Ice-OS is a linux kernel with a stripped down set of GNU utilities and the ICE software framework designed to focus on devIce specific tasks including the ICE web services.

Includes:

krn : linux 4.4.27-2 kernel gnu : busybox and other GNU linux utilities gcc : GNU C and C++ compilers gfc : GNU Fortran compiler jdk : Java JRE and JDK nxm : NeXtMidas framework xm : XMidas framework ice : ICE framework & web server ssh : Secure login and copy vnc : VNC server on :1

Excludes:

wm : Window manager wb : Web Browser sd : SystemD

Configuration:

The Q-Seven CPU has an HDMI, 1GbE, and two USB ports available on the chassis. It boots up for 3 seconds at the network address 192.168.0.123 before moving to its configured address. The network configuration can be changed from the console, an ssh session to root, or via a special ping while booting.

Console:

After booting, the system console port at tty7 switches to tty3 and runs the ICE console application. It is prompting for status, software installation, network configuration, server applicaion start & stop, system reboot & poweroff, or VNC display on the HDMI port. With a monitor and keyboard plugged into the HDMI and USB ports, this interface is always available. This is also the system monitor displaying boot progress and other system messages.

If you know the current address of a devIce, ssh to the root account and run "ice console" from there. If you do not know the current address, connect the devIce's ethernet to another computer running the ICE software tree. From that node, run "nM> iceconsole/sendping/addr=x/mask=y/gw=z" to start the special boot ping, and then boot the target devIce to configure it with the x, y, and z addresses for x=IPAddr, y=netMask, and z=Gateway. Make sure the sending machine can see the 192.168.0.x network.

Application:

The script /home/iceman/iceserver is run at boot time after all resources are enabled. The default script starts the iceserver using the file icebox.tbl as the configuration file. This file determines whether the application starts on its own or waits for controls to be sent over the web interface.

To view the running iceman application, open a web browser to http://<addr>:8080 or a VNC client session to <addr>:1.

If the application is not a SNAPAPP table configured application and you need it to start automatically at boot, modify this script to include your startup.

Accounts:

The IceOS is preconfigured with 1 root and 3 user accounts:

The iceman account automatically starts a VNC session and runs the NeXtMidas iceserver application on bootup. This is configured by the icebox.tbl file in /home/iceman/icebox.tbl. To change the configuration, use scp to copy over this file and reboot the devIce, or use stop/start from the console. To disable the automatic startup rename or remove the iceserver script from the iceman login directory. This account runs entirely off of the readonly partition. It cannot be damaged by inadvertant power-offs.

The xmidas account runs the cshell for a user supplied XMidas application. XMidas is started by xms. The xmidas build uses gcc and gfortran. The user option trees should be added under /user/opt/ with the proper adjustments to xmstartup. The xmidas software is entirely on the writable partition /user.

The icemkr account is used to build NeXtMidas or XMidas software. The trees are owned by this user and will err if either iceman or xmidas attempt to build there. Do not change permissions to these trees. To start NeXtMidas, type nms. To start xmidas from the icemkr account, you will need to type csh first, then type xms.

The user accounts all default their DISPLAY variable to :1 which is where the web server gets its displays. If you ssh into the devIce you should set your display variable to the address you are ssh'ing from such as DISPLAY=192.168.0.70:0 for example.

Terminals:

The inittab is configured to launch 4 TTYs. The system console boots up on TTY7 then switches to the Ice Console program on TTY3. TTY's 1-2 are open for user logins. To switch between TTYs, use Alt F1-3 or Alt F7.

Rebuild:

If your devIce's disk becomes corrupt, insert a USB stick containing IceOS and select that UEFI partition as the first position in the boot order in the BIOS. Then boot the device. It should show as booting from MD_BOOT_ (usb drive) not MD_BOOT (internal drive). If this succeeds, it should boot to the ICE console: Select INSTALL from the menu. When completed, select POWEROFF. When powered off, remove the USB stick and press the reset button or cycle the power. At this point any user configuration changes will need to be redone.

IOC - This file contains a brief text description of the currently available code

Go to full page: ICE_Help_IOC

This file contains a brief text description of the currently available code downloads for the Altera IOC (I/O Controller) Chip. Standard Input/Output configurations handle packing/unpacking of 1|4|8|16 bit data words, gating, triggering, embedded timecode, and module programming.

The mux clock options are controlled by the MUXCLK=s flag. See Help on MUXCLK flag.

II - Mod1=StdInput Mod2=StdInput
IIX - Mod1=StdInput Mod2=StdInput with mux clock
IIR - Mod1=StdInput Mod2=StdInput with internally generated ramp
IIS - Mod1=SDDSInput Mod2=SDDSInput with packet handlers
IO - Mod1=StdInput Mod2=StdOutput
IOX - Mod1=StdInput Mod2=StdOutput with mux clock
OO - Mod1=StdOutput Mod2=StdOutput
OOY - Mod1=StdOutput Mod2=StdOutput with independent clocks

OOW - Mod1&2 internally generated white noise with timecode
T1 - Test internal loopback module 2 out to module 1 in
T2 - Test internal loopback module 1 out to module 2 in

E321 - Dual E3 to 16xE1 Demux w/ optional sync
8E1 - Dual asynchronous 8 clock/data pairs
GSM - Dual E1 channelizer/unpacker
FMDE - Handles framing of FMDE signals
BP - Handles bit packing of 1,2,3,4,5,6,7 or 8 bit data

The Standard Input/Output configurations are loaded automatically during a pic_reset according to the specified module configuration. The non-standard IOC downloads can be performed during a reset using the IOC=xxxx flag, or after a reset by calling pic_loadfile. From Midas, this is an optional parameter on PICDRIVER, ie: PICD RESET PIC1 8E1

For PIC5 and later cards, the IOC= setting is not actually a FPGA download file, but a register setting in the SoC download to implement that function. The specific algorithms E321 ... BP would be handled in FPGA cores loaded onto processor modules or the main board in some cases.

SOC - This file contains a brief text description of the currently available code

Go to full page: ICE_Help_SOC

This file contains a brief text description of the currently available code downloads for the Xilinx System On a Chip FPGAs.

Processor Modules implement the module control/data interface, memory controller, specialty chip (tuner) interfaces, and processor cores in a single Virtex chip.

The 5+ series cards implement the PCI interface, module control/data interfaces, memory controller, processor cores, and IO controller in a single Virtex chip.

The SOC's IO controller implements all of the IOC modes in the default load. The IOC=s settings that are downloads on pre series 5 cards are operational register sets on series 5+ cards.

All SoC downloads contain a 4-character configuration signature. The first two characters describe the I/O or processor module interface types. The third and fourth characters specify the internal functional cores 1 & 2. If the fourth character is blank, it is the same as core 1.

The supported I/O module interface configurations are

S: SingleEnded used for E2D,D2E, T2D,D2T, LV2D,D2LV, A2DR8,D2AR8 modules.
D: Differential used for DR2D, RFXD, A2DR14
H: HyperTransport used for SNTR5XD, SDDSXD,TGSDDSXD, A2DR9,D2AR9, A2DR10,A2DR11,A2DR13, LB2D modules.
R: RocketIO used for MSASXD, DSFPXD

The processor module data interface configurations are

S: SingleEnded used for modules on PIC4X 
H: HyperTransport used for modules on PIC5 and later

The supported Core configurations are

N: Noop Engine 
F: Filter Engine 
D: Demod (2-D LUT) Engine (default on DTDMs)
T: Tune/Filter/Decimate/Resample/Demod Engine (default on PICs)
U: User Engine (Customer specific Upsampler in current release)
V: Vita-49 Radio Transport
G: GSM Engine

The currently supported combinations of I/O and Core configurations are

SS - Mod1=SingleEnded Mod2=SingleEnded
HH - Mod1=HyperTransport Mod2=HyperTransport 
SH - Mod1=SingleEnded Mod2=HyperTransport 
SSN - Mod1=SingleEnded Mod2=SingleEnded Core=Noop
HHN - Mod1=HyperTransport Mod2=HyperTransport Core=Noop
HHF - Mod1=HyperTransport Mod2=HyperTransport Core=Filter
HHTF - Mod1=HyperTransport Mod2=HyperTransport Core1=Tuner Core2=Filter
HHTQ - Mod1=HyperTransport Mod2=HyperTransport Core1=Tuner Core2=QuickTuner

The SoC code is programmed into the FPGA's boot EPROM with the flash utility.

For example, PICDRIVER LOADFLASH PIC1 ICEPIC5_SSN

This takes roughly three minutes. Take note of the verification info. If this reads back with zero errors, you are ready to reboot the card.

If there are errors, do NOT power off or reboot. Repeat the loadflash until it returns with zero errors. If the card is rebooted with a bad flash, please call the factory. You will have to return it or use a 2nd PIC5+ card to reload the dead card's flash. This involves a standard 14 pin JTAG cable with special jumper settings.

Linux systems can use a live reboot feature to reload the SOC.

For example, PICDRIVER SET PIC1 FLASH 999

All other systems will need to power down the machine, and reboot. To verify the reboot use PICDRIVER DETECT. The output will look something like

nM> pic detect
CARD #0 Type=PIC4  (Up/Idle)
Interface  Type=PCI ChipRev=9 Bus=32b Clk=33MHz  Endian=0 Driver=317
Modules    Iom1=UNKNOWN Iom2=UNKNOWN
FirmWare   Proc=318 Ioc=OOW
CARD #1 Type=PIC5  (Up/Idle)
Interface  Type=PCI ChipRev=3 Bus=64b Clk=66MHz+ Endian=0 Driver=317
Modules    Iom1=NONE Iom2=NONE Pm1=DTDMX:DEF  Pm2=DTDM:DEF
FirmWare   Proc=318 Ioc=II   SoC Ver=318 Sig=HH

The Soc version and signature line should show the new load.

Each SoC flash for an ICE release has an associated CRC value. See the release notes section on NON-VOLATILE for the procedure to validate the currently loaded flash CRC.

PCI - This file contains a brief text description of the currently available EPROM

Go to full page: ICE_Help_PCI

This file contains a brief text description of the currently available EPROM revisions for the PCI Controller Chip.

PIC5+ - What's different about the new cards
CHECK - How to check the current PCI chip EPROM revision
V2 - Original EPROM revision for the PIC2, PIC3T, MBT3, and SLIC3
V5 - Upgrade EPROM revision for the PIC2, PIC3T, MBT3, and SLIC3
V6 - Original EPROM revision for the PIC4T and PIC4X
V7 - Modified EPROM revision for the PIC4Tr7
V8 - Modified EPROM revision for the PIC4Tr7 and PIC4Xr8
V9 - Modified EPROM revision for the PIC4Tr7 and greater.
UPGRADE - How to upgrade the PCI EPROM

GPS - This file contains a brief text description of the currently available services

Go to full page: ICE_Help_GPS

This file contains a brief text description of the currently available services provided by the GPS IO module. This module uses a Conner Winfield Wi125 GPS receiver to train a 10MHz VCO frequency reference and generate 1PPS and IRIG-B timing outputs. The 1PPS is synchronous to the 10MHz reference. The control loop for this circuit is handled by a JVM on the module's FPGA running $ICELIB/lib/IceGPS.java.

To retrieve the GPSDAT results from a SNAPPER/SERVER=9001/GPS=2 with a GPS module on the 2nd IO module site:

nM> icenet get nic1x "GPSDAT" "RTAB"

To get just the seconds of Year from the GPSDAT result which is itself a table into the local results named mysoy:

nM> icenet get nic1x "GPSDAT.SOY" "RTAB"  /label=mysoy

To start a GPS server on an ICE card with a GPS module on the MODULE2 site:

nM> pic/server=9009 GPS pic1auto

or from a batch script:

$NMROOT/os/nmbat PIC/SERVER=9009/GPS=2 GPS PIC1AUTO

CRCS - PIC5:

Go to full page: ICE_Help_CRCS

PIC5: LoadFlash File=ICEPIC5_SS CRC=0xA8150950 LoadFlash File=ICEPIC5_DD CRC=0x3EE2E3D8 LoadFlash File=ICEPIC5_HH CRC=0x00C42593 LoadFlash File=ICEPIC5_SH CRC=0x89D41BA1 LoadFlash File=ICEPIC5_DH CRC=0x8282A9B4 LoadFlash File=ICEPIC5_DS CRC=0xDE0CC191

PIC6: LoadFlash File=ICEPIC6_SS CRC=0x659D489C LoadFlash File=ICEPIC6_DD CRC=0x53661F99 LoadFlash File=ICEPIC6_HH CRC=0xA70782DC LoadFlash File=ICEPIC6_SH CRC=0x39E4EF87 LoadFlash File=ICEPIC6_DH CRC=0xACFB072A LoadFlash File=ICEPIC6_HHV CRC=0xB5F4871A LoadFlash File=ICEPIC6_HHTQ CRC=0x3652ECB0 LoadFlash File=ICEPIC6_RRN CRC=0x5CE7667F

POD6: LoadFlash File=ICEPOD6_DD CRC=0x4A9FFF82 LoadFlash File=ICEPOD6_HH CRC=0xCD381971 LoadFlash File=ICEPOD6_RRN CRC=0x242DE504

PIC7: LoadFlash File=ICEPIC7_HH CRC=0x69185D41 LoadFlash File=ICEPIC7_DD CRC=0x2DAA0B96 LoadFlash File=ICEPIC7_SS CRC=0xB847FA49 LoadFlash File=ICEPIC7_DH CRC=0xC275ABB2

PIC8: LoadFlash File=ICEPIC8_HH CRC=0x04F94B2A LoadFlash File=ICEPIC8_HHX CRC=0x5E463A11 LoadFlash File=ICEPIC8_SS CRC=0xF220C33A LoadFlash File=ICEPIC8_DD CRC=0xC6B61A0C

POD8: LoadFlash File=ICEPOD8_HH CRC=0x39B48934

PAC8: LoadFlash File=ICEPAC8_HH CRC=0xB99675BD LoadFlash File=ICEPAC8_HHTD CRC=0x4BB58F30

STATUS - Newer ICE products often involve systems and cards that may be polled for status.

Go to full page: ICE_Help_STATUS

Newer ICE products often involve systems and cards that may be polled for status.

SERVICE - communications with ICE services using SNAPAPP or SNAPPER macros
DRIVER - status of the ICE cards via the driver interface

PACKETS - As network interfaces play an increasing role in data distribution, software

Go to full page: ICE_Help_PACKETS

As network interfaces play an increasing role in data distribution, software and hardware must be extended to process data packets. Three forms of packets are currently handled by the ICE hardware/software:

1. ICE Packet format - 64by header, fixed or variable length data
2. SDDS Packet format - 56by header, fixed 1024by data
3. VRT Packet format - 32by header, fixed 1440by data
4. RMIF Packet protocol - 8by header, variable data

Normally, the packet headers precede the packet data they describe. They may also be placed in separate streams. The packet header formats are as follows:

ICE - ICE Packet Header (Little/Big Endian):
VRT - VITA-49 Radio Transport Packet Header (Big Endian)
SDDS - SDDS Packet Header Modified (Big Endian):
RMIF - RMIF Packet Header (Endian independent):
NETWORK - Network interface notes

SRVICE - This file contains a text description of the application srvice.

Go to full page: ICE_Help_SRVICE

This file contains a text description of the application srvice. in the test subdirectory of the ICE tree. It is a C program that reads in simple script files to control basic functions of an ICE card including configuration, reset, dma, fileIO, and status.

If the filename has the form port=xxxx, a network socket is setup on the specified port to receive command lines from a remote client.

The script files treat any line starting with a !, /, or # as a comment. White space is trimmed from the front and back of each line. Tokens are delimited by a white space, usually 2 or 3 per line. The first token is the command followed by 1 or more arguments. Valid commands and their arguments are:

CARD N config		! defines configuration of card number N
RESET N1 N2	 	! reset cards N1 through N2
DMA M config		! defines configuration of DMA channel M
CORE M config		! run the configured CORE setup parameters on DMA channel M
LOADFC M file		! load the filter coefficients onto DMA channel M 
START M1 M2		! starts DMA channels M1 through M2
PAUSE sec		! pause the indicated number of seconds
WAIT M		! wait for DMA channel M to complete
STOP M1 M2		! stops DMA channels M1 through M2
SET M keyname value	! set run time parameter
GET M keyname value	! get run time parameter

The CARD and DMA indices N and M can be 0 or 1 based.

The CARD config string is stored by index for use in the RESET and DMA commands. The string is passed as is to the RESET routine, and substituted for the CARD=N in the DMA command config string. This config string is passed to pic_open() for that operation.

The RESET command performs a pic_reset() on card indices N1 through N2. If N2 is not supplied, it defaults to N1.

The DMA command sets up a DMA channel operation. The config string contains a list of flags using a key=value syntax to define the operation. Pertinent flags are:

CARD=N		! config string for card N is inserted here
PORT=port		! port on card to use (ie. MODULE1,TUNER2,TBANK21)
RATE=rate		! sample rate in Hertz
BITS=bits		! sample size in bits
LENGTH=len		! length of circular memory buffer in seconds (def=1)
FREQ=freq		! center frequency int Hertz for tuner
DEC=dec		! decimation for tuner (def=1)
GAIN=gain		! gain in dB for tuner (def=0)
DIR=io		! direction of transfer (-1=input 1=output) (def=-1)
XFER=xlen		! transfer length in bytes
SKIP=skip		! only capture every skip frames where frame=XFER 
FUNC=func		! argument to pic_dmafunc() (-2=continuous, >0=#passes)
FILE=filename		! filename to write into or read from
PKT=pktype		! output pktype=ICE|SDDS|VRT packets (FILE=udp:address)

A list of all flags available may be found in flags.hlp. These include CFIR, PFIR, and RFIR for loading filter taps.

The CORE command runs the setup for a CORE as described by the ICECORE paradigm. The syntax for this may be found in jvcc.hlp.

The LOADFC command loads the filter coefficients found in the file into the designated tuner of filter core. The tuner filter location CFIR, RFIR, or PFIR is determined by the filter length.

The START command starts a thread for each dma indices M1 through M2. If M2 is not supplied, it defaults to M1.

The PAUSE command pauses the script for the specified number of seconds. This is intended to be used for testing purposes only.

The WAIT command waits for a thread for dma on index M to complete. If M = -1, it waits for a user keypress.

The STOP command stops the thread performing a dma on indices M1 through M2. If M2 is not supplied, it defaults to M1.

The SET and GET commands will set or get any of the named keys found in keys.hlp. If keyname begins with '0x', it is assumed to be a core control register offset for that DMA channel.

At the end of the script, all cards are closed before exiting.

Here is an example script:

!!!!!!!!!!!!!!!!!!!!!!!!! ! Example srvice script ! CARD=x in DMA subs that into config !!!!!!!!!!!!!!!!!!!!!!!!! CARD 0 ICEPIC,DEVNO=0,IOM1=LB2DR3,IOM2=D2AWGR3,MUXCLK=P, CARD 1 ICEPIC,DEVNO=2,IOM1=LB2DR3,IOM2=D2RF,MUXCLK=P, RESET 0 1 DMA 0 CARD=0,PORT=PM0TUNER1,RATE=100e6,BITS=-16,LENGTH=1,DEC=4,MBITS=-16,RFFREQ=950,RFBW=40,RFGAIN=15,RFOPTS=(ENABLE|DCS|AIS|LNA|XREF),XMTGO,TC=CPUP0 DMA 1 CARD=0,PORT=MODULE2,RATE=25e6,BITS=-16,LENGTH=1,DIR=1,RFFREQ=70,RFATTEN=0 DMA 2 CARD=1,PORT=PM0TUNER1,RATE=100e6,BITS=-16,LENGTH=1,DEC=4,MBITS=-16,RFFREQ=950,RFBW=40,RFGAIN=15,RFOPTS=(ENABLE|DCS|AIS|LNA|XREF),XMTGO,TC=CPUP0 DMA 3 CARD=1,PORT=MODULE2,RATE=25e6,BITS=-16,LENGTH=1,DIR=1,RFFREQ=70,RFATTEN=0 START 0 3 PAUSE 1 SET 0 FREQ 1.23e6 PAUSE 1 SET 0 GAIN -6 WAIT STOP 0 3

NETWORK - Newer ICE products often involve data capture/playback over standard host network interfaces.

Go to full page: ICE_Help_NETWORK

Newer ICE products often involve data capture/playback over standard host network interfaces.

SETUP - system setup parameters
SERVICE - communications with ICE services using SNAPAPP or SNAPPER macros
ICENET - utility for communicating with ICE services macro from outside Midas

RELEASE - A listing of the release notes for the current ICE Option Tree release.

Go to full page: ICE_Help_RELEASE

A listing of the release notes for the current ICE Option Tree release.

NEW_FEATURES - New Features (this release only)
BUGS_FIXED - Bugs fixed (current release only)
WHAT_MIGHT_BREAK - Possible gotchas (current release only)

Other discussions pertinent to all ICE releases.

NONVOLATILE - Non-Volatile EEPROM Signatures for Series-5/6 Cards
COMPATIBILITY - Compatibility Guidelines
BIRTHDATE - Hardware / Software Compatibility 

A listing of release notes for all previous versions of the ICE tree.

NEW_FEATURES_ALL - New Features (all previous releases)
BUGS_FIXED_ALL - Bugs fixed (all previous releases)
WHAT_MIGHT_BREAK_ALL - Possible gotchas (all previous releases)