ICE Help KEYS

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Summary: Key names for accessing parameters

This file covers all of the keyed parameters that one can set or get using the pic_getKey() and pic_setKey() routines. Unless specifically noted, all keys are of type int_4.

From Midas these can be called with

PICDRIVER GET <alias> <key> <label>

and

PICDRIVER SET <alias> <key> <value>

From C, Fortran, or Java code, the include file key name defines are formed by prepending KEY_ to the name of the key.

When an index field is required, it is infered from the /PORT=xxx switch or PORT=xxx flag in the card alias. If the PORT is not specified, the /DMAC=n switch provides the index. For an index that does not relate to a DMA channel, such as the TEMP key, use the negative of the index. This bypasses the DMA channel lookup for a port index.

Many of these functions are also supported as flags in the configuration string or /FLAGS=(string) switch. See PIC HELP FLAGS.

The currently supported keys are:

RATE - Input sample rate in Hz

Input sample rate in Hz

FREQ - Tuned frequency/nyquist (double)

Tuned frequency/nyquist (double)

NFREQ - Return the nearest actual tuned frequency/nyquist available.

Return the nearest actual tuned frequency/nyquist available. Use only with pic_getkey and prefill the value with the desired amount.

DFREQ - Channel spacing for tuner banks frequency/nyquist (double)

Channel spacing for tuner banks frequency/nyquist (double)

DEC - Tuner decimation (or frame decimation 1-1024)

Tuner decimation (or frame decimation 1-1024)

NDEC - Return the nearest actual tuner decimation available

Return the nearest actual tuner decimation available Use only with pic_getkey and prefill the value with the desired amount.

GAIN - Tuner gain in dB (must be set after loading user filter coefficients)

Tuner gain in dB (must be set after loading user filter coefficients)

EMT - Envelope Measure and Track.

Envelope Measure and Track. of the magnitude of the high byte of the input samples. This is an estimate of the current loading of signal from 0 to 128. A vaule of 75 to 100 is reasonable loading for an A2D in most environments. Setting this key adjusts the parameters for the EMT function as described in the EMT flag help file. This function is performed on the base card so it can be used behind analog or digital modules.

ADLM - A2D Load Monitor of signal at input of A2D.

A2D Load Monitor of signal at input of A2D.

MGAIN - Module gain in dB when module has adjustable gain block (typically analog)

Module gain in dB when module has adjustable gain block (typically analog)

MFREQ - Module center frequency in Hz when module is able to perform a real-to-complex conversion and shift

Module center frequency in Hz when module is able to perform a real-to-complex conversion and shift

OVSR - Tuner over-sampling rate

Tuner over-sampling rate

RATIO - Tuner resampler ratio (resamplerOutputRate/tunerOutputRate) (double)

Tuner resampler ratio (resamplerOutputRate/tunerOutputRate) (double) If using PRESAMP, this must be set on dmac=0 before the call to N=pic_ioport(...) If using RESAMP, this must be set on dmac=N after the call to N=pic_ioport(...) where N is the dma channel of the tuner of interest.

NRATIO - Return the nearest actual tuner resampler ratio available (double)

Return the nearest actual tuner resampler ratio available (double) Use only with pic_getkey and prefill the value with the desired amount. Graychips use a 26 bit modulo register. FPGA tuner uses 28 bit with M/N phase reset circuit.

FRAME - Frame size (32 <= 2**N <= 512K) for IOC framed decimation (PIC3 and earlier)

Frame size (32 <= 2**N <= 512K) for IOC framed decimation (PIC3 and earlier) Frame size (256 <= N*256 <= 512K) for IOC framed decimation (PIC4 and MBT4) Frame size (64 <= N*64 <= 512K) for IOC framed decimation (PIC5 and later)

PKTLEN - Packet length for tuner bank frames in bytes

Packet length for tuner bank frames in bytes

CHAIN - Set DMA chain pointer to specified index (or address)

Set DMA chain pointer to specified index (or address) Get the next chain pointer index

ACTIVE - Reports number of active DMA channels on card, -1 if not reset, -2 if locked

Reports number of active DMA channels on card, -1 if not reset, -2 if locked

DELAY - Delay in some applications (in samples)

Delay in some applications (in samples)

TCMODE - TimeCode Mode index (debug)

TimeCode Mode index (debug) The current supported timecode modes are:

TCM_OFF 0
TCM_CPU 1
TCM_ZTC 2
TCM_SDN 3
TCM_SMS 4
TCM_DTL 5
TCM_IRB 6
TCM_SDD 7
TCM_ICE 8
TCM_VRT 9
TCM_FILE 10

TCOFF - TimeCode offset in Seconds Of Year for applicable output modules.

TimeCode offset in Seconds Of Year for applicable output modules.

RFFREQ - RF Module frequency in MHz (double)

RF Module frequency in MHz (double)

RFBW - RF Module bandwidth in MHz (double)

RF Module bandwidth in MHz (double)

RFATTN - RF Module attenuation in dB

RF Module attenuation in dB

RFGAIN - RF Module gain in dB

RF Module gain in dB

RFOPTS - RF Module options mask (See FLAGS)

RF Module options mask (See FLAGS)

RFPWR - RF Module input power measurement in dB

RF Module input power measurement in dB

FLGBSET - Set specified bits in the common flags

Set specified bits in the common flags

FLGBCLR - Clear specified bits in the common flags

Clear specified bits in the common flags

TFLGBSET - Set specified bits in the tuner flags

Set specified bits in the tuner flags

TFLGBCLR - Clear specified bits in the tuner flags

Clear specified bits in the tuner flags

FLAG - Returns the FLAG field of the indexed DMA structure.

Returns the FLAG field of the indexed DMA structure.

DRVFLG - Returns the FLAG field of the driver status page.

Returns the FLAG field of the driver status page. This status is a bit mask of 10MHz, 1PPS, and IRIG signal status on various ports on a card.

IPVLAN - Set the IP VLAN address of an ethernet module

Set the IP VLAN address of an ethernet module

IPADDR - Set the IP address of an ethernet module

Set the IP address of an ethernet module

IPCONN - Connect to a particular IP multicast port

Connect to a particular IP multicast port

IPDISC - Disconnect from a particular IP multicast port

Disconnect from a particular IP multicast port

PKTHDR - Return the contents of the last ICE/SDDS packet header.

Return the contents of the last ICE/SDDS packet header. See ICEROOT/inc/packets.h for a mapping of this 64 byte data structure. If the VERBOSE flag is set when retrieving this key, a hex dump will print out.

SEQERR - Return the running count of SDDS sequence gaps

Return the running count of SDDS sequence gaps

SEQFILL - Return the running count of SDDS sequence gaps filled by I/O processor.

Return the running count of SDDS sequence gaps filled by I/O processor. These are not accounted as sequence errors by SEQERR.

ALG - Active algorithm (by index)

Active algorithm (by index)

ARGS - Algorithm arguments offset

Algorithm arguments offset

CLKI - Invert the clock

Invert the clock

MSBI - Invert the Most Significant Bit

Invert the Most Significant Bit

BIT - Bit# for bit serial acquisition (0,1,4,15)

Bit# for bit serial acquisition (0,1,4,15)

BITS - Number of bits for acquisition (1,8,16)

Number of bits for acquisition (1,8,16)

CTYPE - Card type (2=PIC2 3=PIC3 4=PIC4 8=MBT2 9=MBT3 12=SLIC3)

Card type (2=PIC2 3=PIC3 4=PIC4 8=MBT2 9=MBT3 12=SLIC3)

PTYPE - Port type (1=SERIAL 2=LINK 3=MODULE 4=TUNER)

Port type (1=SERIAL 2=LINK 3=MODULE 4=TUNER)

PINDEX - Port index 1,2,3,4.

Port index 1,2,3,4.

MTYPE - IO module type (-1=A2D 1=D2A -2=E2D 2=D2E etc.

IO module type (-1=A2D 1=D2A -2=E2D 2=D2E etc.

MTYPE1 - IO module#1 type

IO module#1 type

MTYPE2 - IO module#2 type

IO module#2 type

PMTYPE - Processor module type (1=DTDM 2=DTDMX etc.

Processor module type (1=DTDM 2=DTDMX etc.

PMTYPE1 - Processor module#1 type

Processor module#1 type

PMTYPE2 - Processor module#2 type

Processor module#2 type

PMINDEX - Processor module index (active selection) 0=PIC 1=PM1 2=PM2

Processor module index (active selection) 0=PIC 1=PM1 2=PM2

MCHNS - Maximum number of tuner channels on board 0-24

Maximum number of tuner channels on board 0-24

CHNS - Number of usable tuner channels 0-24 (uses CPC setting)

Number of usable tuner channels 0-24 (uses CPC setting)

CHAN - Select channel in a tuner bank.

Select channel in a tuner bank.

CPC - Channels per chip to use 1|2|4 (graychips only)

Channels per chip to use 1|2|4 (graychips only)

TCINC - Adjacent tuner channel increment (to next tuner on same side)

Adjacent tuner channel increment (to next tuner on same side)

IOCTYPE - Type of current IOC load module (i.

Type of current IOC load module (i.

CBUFSZ - Default buffer size on card for specified port

Default buffer size on card for specified port

STATUS - Current card DMA, ROUTE, and SYSTEM status

Current card DMA, ROUTE, and SYSTEM status On ICEPODs setting this uses the lower 8 bits to conditionally illuminate the 8 front panel LEDs

ROUTE - Current FPGA routing register

Current FPGA routing register

DETECT - Auto detect the current card configuration where the dmac argument is the device number or -1 for all.

Auto detect the current card configuration where the dmac argument is the device number or -1 for all.

PRCCLK - PRoCessor clock rate

PRoCessor clock rate

IOCCLK - IO Controller chip clock rate

IO Controller chip clock rate

ICLK - IOC Internal divide clock rate (MUXCLK=I)

IOC Internal divide clock rate (MUXCLK=I)

PCLK - Programmable clock (MUXCLK=P)

Programmable clock (MUXCLK=P)

CCLK - Motherboard socketed crystal rate (MUXCLK=C)

Motherboard socketed crystal rate (MUXCLK=C)

MCLK - Measurement of clock rate of the specified clock configuration.

Measurement of clock rate of the specified clock configuration. It cannot be executed on a running port.

PCICLK - PCI clock rate (33|66|100|133) MHz

PCI clock rate (33|66|100|133) MHz

PCIBUS - PCI bus width (32|64) bits

PCI bus width (32|64) bits

PCIBW - PCI bus bandwidth in Mby/s (theoretical)

PCI bus bandwidth in Mby/s (theoretical)

PCIREV - PCI controller chip EPROM rev

PCI controller chip EPROM rev

DRIVER - ICE driver version running on this machine

ICE driver version running on this machine

VERSION - ICE software version loaded on this card

ICE software version loaded on this card

FPGAREV - ICE FPGA firmware versions loaded on this card

ICE FPGA firmware versions loaded on this card

dmac=0 Base card SoC firmware version (via flashable EPROM)
1 I/O module #1 firmware version
2 I/O module #2 firmware version
7 Processor module #1 firmware version
8 Processor module #2 firmware version

FPGASIG - ICE FPGA firmware signature loaded on this card

ICE FPGA firmware signature loaded on this card

dmac=0 Base card SoC firmware signature (via flashable EPROM)
1 I/O module #1 firmware signature
2 I/O module #2 firmware signature
7 Processor module #1 firmware signature
8 Processor module #2 firmware signature

RSTIME - get time of last reset

Time of last card reset (index=0) or I/O port reset (index=1|2) in J1950 seconds. A card reset also updates the two I/O port registers, but the individual I/O ports may be reset at any time without a full card reset.

PFIFO - PCI Side FiFo (debug)

PCI Side FiFo (debug)

AFIFO - Card/Adon Side FiFo (debug)

Card/Adon Side FiFo (debug)

IOC - IOC registers

IOC registers

IOCIOM - IOC IO Module control register

IOC IO Module control register

IOCALG - IOC algorithm register offset

IOC algorithm register offset

IOCRAM - IOC RAM register offset

IOC RAM register offset

MOD - IO Module register offset

IO Module register offset

CORE - Processing core register offset.

Processing core register offset. Cores are signal processing algorithms implemented in FPGA code. Core registers are byte addressable but always 4 bytes wide. To address a register, add the bytes offset to the KEY_CORE parameter. The window is 32Kby wide.

APP - Application register offset.

Application register offset. Apps are signal processing algorithms implemented in PPC|SHARC processor code. Application registers are byte addressable but always 4 bytes wide. To address a register, add the bytes offset to the KEY_APP parameter. The window is 4Kby wide.

TEMP - Get temperature measurements from port.

Get temperature measurements from port. This key retrieves temperature data from the System Monitor of various FPGAs attached to the pic board. Use the index field as follows:

0 - the mainboard (PIC7+)
1,2 - the IO Modules
5   - the board temp (POD6+)
7,8 - the Processor Modules

The temperature is returned in degrees Celsius.

SYSMON - Get temperature/voltage measurements from port.

Get temperature/voltage measurements from port.

This key retrieves data from the System Monitor of various FPGAs attached to the pic board. Use the index field as follows:

0 - the mainboard (PIC7+)
1,2 - the IO Modules
7,8 - the Processor Modules

The verbose flag causes text output to be displayed.

TPOE - Test port output enable on series 5+ cards

A runtime method for enabling the test port. See help FLAGS TPOE

TPD - Test port data

A runtime method for reading the current contents of the test port. The default TPOE=1 test port selects the auxiliary module. The current contents of this test vector are

bit=0  MGO	- master enable of a port, used to trigger another port or card
=1  XSYNCI - the input of the eXternal sync port (needs DC coupled input jumpers 1&3)
=2  TSYNCI - the input trigger bit, usually bit0 of IOModule 1
=3  OPPMS  - a one pulse per millisecond timer
=4  PWR5V  - enable for the IO Module's 5V power brick
=5  TBD
=6  TBD
=7  PCREF  - 10MHz reference for the programmable clock

TPDX - Test port data change

Reads the whether there has been a low to high transition on each bit in the test vector since the last read of TPD or TPDX.

TPSR - Test port status register

Read and/or write the 8-bit Test Port Status Register in the testport FPGA module. This enables user control of the status LEDs on an Ice-Pod. Valid bitmask is 0-255. Set to -1 to disable status register output (reenables the silon LED mode on Ice-Pods)

JTAGPORT - JTAG cable debug port assignment on series 5+ cards

A runtime method for connecting the main board JTAG cable connector to one of the I/O or Processor module sites. This allows a developer to use chipscope or other JTAG base debuggers on the module. Port numbers are:

1 - I/O Module 1
2 - I/O Module 2
7 - Processor Module 1
8 - Processor Module 2

The include file names are formed by prepending KEY_.

MPCIO - Multi-Purpose Chip I/O register.

Multi-Purpose Chip I/O register. This register controls the 4-bit multi-purpose chip I/O bus. The bottom 4 bits are the data values. The upper 4-bits are their respective output enables. On the ICEPOD-6 the bits are as follows: 0. UID Chip clk 1. UID Chip data 2. USB 0 data/power enable 3. USB 1 data/power enable

CUID - get the UID Chip 8-byte value

Returns a unique 8-byte value for this hardware.

HWREV - get the ICE Hardware Revision 4-byte value

Returns a 4-byte board revision for this hardware.

/dmac=-5  Crossbar
/dmac=-11  PM 1
/dmac=-12  PM 2
/dmac=0 Board EPROM ID

EVCNT - get the 2 16-bit event counters

Returns a 2 16 bit event counters packed into 1 4-byte value.

RTCLK - gets the 8-byte RealTime Clock value.

Returns an 8-byte value for the RealTime Clock chip if battery backup is enabled.

GPS - gets the time and position from an ICE-GPS IO Module

Returns an array of 6 doubles as (time,lat,lon,alt,status,nos) where time is in SecondsOfYear, lat and lon are in degrees, and altitude is in meters. Status is 0=GPS off, 6=GPS track, and nos is the number of satellites in view.

DUMP - Dumps debug info to the screen for specific cores and modules.

Dumps debug info to the screen for specific cores and modules.

Some modules, including the GPS, output even more info when accompanied by the VERBOSE flag. The GPS module also waits for the next one-PPS to occur so it can be put in a forall loop as a status display.

All internal cores have a predifined set of registers that will dump to the screen as well. Parameter #0 is the core signature, a 4-byte ascii code for the algorithm. Parameter #7 is the clockrate the core was compiled with. All other parameters are core specific.

Use /CORE=n on the picdriver command to select which core to dump.

(11-14 for PM1, 21-24 for PM2, 41-44 for PM0 cores)

There are a special set of flags to control the register dump:

CPN=n Number of registers to dump (def=8)
CPW=n Width of registers in bytes (def=4)
CPO=n Offset of first register (def=0)
CPS=n Stride between registers (def=4)

MGTDUMP - Dumps debug info to the screen for specific GigaBit Transceivers.

Dumps debug info to the screen for specific GigaBit Transceivers. If dmac>0 uses dump_mgt, if dmac<0 uses dump_rio

dmac>0:  0=CB-PCIe 10=CB-PMs 11=PM1-CB 12=PM2-CB
dmac<0:  10=CB-PMs 11=PM1-CB 12=PM2-CB