ICE Help FLAGS

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Flags are typically specified in the config string with either a comma "," or vertical bar "|" as a separator. They modify the standard behavior of the library routines as noted. The ICE Midas primitives take a FLAGS switch to add flags to the current config string. For instance:

SOURCEPIC/flags=(VHS|MUXCLK=A|MSBI)

NOTE: The flags argument in the ioport() routine are NOT for tuner flags.

The tuner flags must be placed in the config string.  

Clocking

MUXCLK=s - IOC code allowing choice of 6 on-board clock sources

Loads IOC code allowing muxed clock operation. Both modules use the same clock. Outputs always use MUXCLK. There 7 possible sources for the muxed clock signal:

s=N No MUXCLK
s=I Internal clock = 40MHz/N where N is an integer (1-4096)
s=A Module A input clock (or s=1)
s=B Module B input clock (or s=2)
s=C Alternate Crystal on series 3+ cards
s=D Alternate Crystal CCLK/N where N is an integer (1-64), (1-16) on series 3
s=X External clock on series 3+ cards
s=P Programmable Clock on series 4+ cards
s=PX Programmable Clock with eXternal reference (PREFX)

Many newer IO modules (especially analog modules) contain their own programmable clocks. These clocks are not shared as the mainboard MUXCLK is.

Note: Specifying MUXCLK=PX is equivalent to MUXCLK=P with PREFX. See PREFX for details.

INTCLK - Internally generate clock for IO modules (same as MUXCLK=I)

Internally generate clock for IO modules (same as MUXCLK=I)

CLKI - Invert input clock

Input data cycles are defined by the rising edge of the input clock. Data is assumed to be stable in the middle of the cycle. Therefore, data is clocked in on the falling edge of the clock.

This flag may be used to invert the input clock when the data source uses the opposite convention.

Output data cycles are defined by the rising edge of the output clock. Data will change on the rising edge of the clock, and will be stable at the falling edge of this clock. When stopped and during configuration, the clock is high. When enabled, clock goes low. The clock will then go high and low for each valid sample. When disabled, clock will return high.

This flag may be used to invert this clock output convention. Data will change on the falling edge of the clock, and will be stable at the rising edge of the clock. When stopped and during configuration, the clock is high. The clock will then go low and high for each valid sample. When disabled, clock will stay high.

CLKRE - Latch data on Rising Edge of Clock instead of default falling edge.

Latch data on Rising Edge of Clock instead of default falling edge. is for signals whose cycle really starts on the rising edge of the clock but prepared the data on the falling edge such that the clean edge to clock with is also the edge that starts the cycle.

This can also be used to force the latch on the rising edge for other non-standard data/clock skew situations.

NCCLK - Non-continuous clock - ports are enabled even if clock is not present.

Non-continuous clock - ports are enabled even if clock is not present.

Normally, the 1st clock cycle is used to synchronize the enabling of a port. If the input clock is inactive when the transfer is enabled, the use of NCCLK will enable the master/slave/trigger signal without the clock.

Normally, output clocks are continuous once they are started in case there are PLLs on the receiving end. If the receive device can handle a non-continuous clock, this flags can be used to send bursty data from an output port. The SINKPIC throttle modes ONESHOT and ONDEMAND automatically add this flag.

PREFX - This option uses the eXternal or clock pin as a reference for the Programmable Clock

This option uses the eXternal or clock pin as a reference for the Programmable Clock (MUXCLK=P) instead of the internal crystal. It MUST be a stable 10 MHz sine wave present at all times. The Programmable clock is a digital phase lock loop and will maintain a stable phase alignment with the reference clock.

For IO modules that have their own programmable clock (newer analog modules), the 10MHz reference clock must be connected to the clock input on that module.

For older analog modules and most digital modules, the programmable clock is on the mainboard and the 10MHz clock must be connected to the eXternal pin at the center of the PCI card edge plate.

Note: On PIC4 and earlier cards, the PREFX flags must also be present during card reset to load the correct IOC code into the FPGA. PIC5 and later cards do this at runtime. The PREFX flag should always be specified at runtime whether or not it is needed at reset.

Note: When using D2Ar9 modules, the PREFX=f can be used to specify a reference frequency other than the 10MHz default. For instance PREFX=20e6 is necessary to generate clocks above 250MHz. The internal reference is a 10ppm 20MHz crystal.

CCLK=f - Specifies the non-standard value of the CCLK crystal in Hertz.

Specifies the non-standard value of the CCLK crystal in Hertz. The standard 65MHz for series 3 cards, and 100MHz for series 4.

DEGLITCH - Enables deglitch circuit for MUXCLK inputs.

Enables deglitch circuit for MUXCLK inputs. inputs with irregular clocks, such as from a switch matrix in scan mode where the input clock may contain small ( < 4 nanosecond) glitches that can cause unpredictable behavior in the IOC processor. This adds a slight delay of approximately 5 nanoseconds to the input clock. For clocks > 50MHz, the CLKDLY=N or CLKRE flags may be needed to clock the data on a clean edge.

CLKDLY=N - Delays input clock by N nanoseconds for clock/data deskew

Delays the input clock by N nanoseconds (1.2ns taps) to adjust the clock edge to the center of eye pattern on noisy or non-standard input signals. This is usually used with CLKI to clock data on the rising edge delayed by 1/2 wavelength + N nanoseconds. Signals that show skew between the clock edge and data edges by the time they reach the input modules can use this to correct the situation on PIC4/MBT4 cards. Note, the 1/2 wavelength is applied internally when the rising edge is used. The CLKDLY=N value is added to this.

The PIC3/MBT3 cards will clock on the rising or falling edges only but with data/clock skew < 1 ns. These cards should not need any correction up to their maximum sample rate of 65MHz.

PRETRIG=N - Capture N cycles before trigger

This option on a PIC5 will start capture N samples previous to the named TGO, GGO, or XGO triggers, where N is between 0 and 15. Normally, the 1st sample captured is the sample in which the trigger signal went high.

PMTHROTTLE=n - throttles Processor Module output to n Mby/s

This flag is useful in applications where the burst rate from a processor module core or tuner bank is too large for the PCI bus even though the total throughput is not. Set this to produce a safe total throughput. This has been used in applications using the Magma cardbus extender which can throttle the PCI bandwidth to 50-70 Mby/s (in older versions).

Data Routing

MSBI - Invert the Most Significant Bit.

Invert the Most Significant Bit.

LSBX - Replace the LSB with the data on the eXternal sync pin.

Replace the LSB with the data on the eXternal sync pin. used to verify IRIGB timecode or some other digital synchronization signal. Note jumpers 2, 3, and maybe 1 need to be closed for this, see HELP on card.

LSBP - Replace the LSB with the data on the 1PPS sync pin.

Replace the LSB with the data on the 1PPS sync pin. This can be used to verify the 1PPS timecode source on a high speed A2D. Currently only applies to the "hh" signature A2Ds including the A2DR9, R10, R11, and R13.

SPINV - Invert the input spectrum by multiplying every other sample by -1.

Invert the input spectrum by multiplying every other sample by -1. useful if an A2D is used to fold in an SOI above nyquist with an odd number of flips and a tuner is not being used. (PIC5+ only).

BIGEND - Invert the bit packing order on SP data.

Invert the bit packing order on SP data. The first sample is in bit=0, second in bit=1 ... bit=7. With the BIGEND flag, the first sample is bit=7, second sample is bit=6, ... bit=0. When running under X-Midas, the default bit-packing is BIGEND. Under NeXtMidas and non-Midas, the default is little endian.

BIT=n - Which bit for single bit acquisitions (0,1,4, or default=15 the MSB)

Which bit for single bit acquisitions (0,1,4, or default=15 the MSB)

MBITS=n - When using a Tuner or Core port, this can be used to specify a non-default data

When using a Tuner or Core port, this can be used to specify a non-default data width at its input, usually a Module. The default is 16 bits. This can be used to feed byte data (MBITS=8) or complex (MBITS=-16) data by negating the value.

On a PIC5+ series card, simultaneous collects of Module and Tuner port where the Module port is specified as other than 16 bits will need this flag on the Tuner port to match the width of the Module port.

See the help on pic_ioport for details on specifying the number of bits.

NBITS=n - When using a tuner with a presampler, MBITS sets the Module bits (Presampler input)

When using a tuner with a presampler, MBITS sets the Module bits (Presampler input) and NBITS sets the Tuner input bits (Presampler output). This defaults to 16.

MGAIN=n - When using a Tuner or Core port, this can be used to specify the gain setting for the

When using a Tuner or Core port, this can be used to specify the gain setting for the input Module. The default is 0. This will only set the initial gain. To adjust the module gain dynamically, you must open a second handle to the Module directly.

MFREQ=n - When using a Tuner or Core port, this can be used to specify the freq setting for the

When using a Tuner or Core port, this can be used to specify the freq setting for the input Module. The default is 0 or fs/4 if input is complex. It can be used on analog modules that can produce complex data and shift the output to a non fs/4 value, like the A2DM14. This parameter is not adjustable at run-time.

ALT - Use alternate numbered port as source of data.

Use alternate numbered port as source of data. resources from Module2 or even numbered from Module 1). Typically used to run all tuners behind one input module.

A better approach is to use the INP=n flag. See HELP on INP flag.

This option requires the MUXCLK=s flag on series-4 cards.

INP=n - Use input n=1 or input n=2 to feed the port.

Use input n=1 or input n=2 to feed the port.

It is often easier to use than the ALT flag, and sometimes necessary.

If channels on both sides of the card are being used, using this flag on both the even and odd channels gives the card the necessay information to keep the port active for the alternate channels when the same side channels are stopped and started.

This option requires the MUXCLK=s flag on series-4 cards.

PORT=port - This specifies the default port type and index for the pic_ioport() library.

This specifies the default port type and index for the pic_ioport() library. The syntax may also include the processor module index. For example:

PORT=CORE2      - the 2nd FPGA core on the default processor module (generic)
PORT=PM2CORE1   - the 1st FPGA core on processor module 2 (specific)
PORT=PM0TUNER2  - the 2nd tuner on the main board (specific)
PORT=TUNER33    - the 1st tuner on processor module 2 (generic)

The generic port indexing syntax will automatically place the port resource on the preferred module. For instance, if there are two processor modules of the same type defined, the TUNER ports will be spread across them. However, the tuners on the main board (PM0) will not be used. This method properly addresses most use cases.

The specific port indexing syntax allows the user to specify the processor module and the index of the port resource on that module. This is the only way to also use the main board TUNER and CORE resources when a processor module is defined.

See help on PIC_IOPORT for more details. See help on PMI=n .

Port resources that are not IO ports, like TUNERs and COREs, are fed by the MODULE on the same side of the card unless the INP or IPORT flags are used.

IPORT=port - This specifies a non-default input routing for a CORE or TUNER port.

This specifies a non-default input routing for a CORE or TUNER port. the input for a CORE or TUNER is the I/O module on the same side of the card for acquisitions and the HOST for playback. This flag can be used to specify an alternate input. Here are the available routing options for input ports:

Module    IPORT=MODULEx       
Tuner     IPORT=MODULEx|COREx
Core      IPORT=MODULEx|COREx|MCOREx|TUNERx|TBANKx

where x is the port index, and the first entry in the list is the default. By default a CORE, MCORE, TUNER, or TBANK is assumed to be on the same processor module as the PORT. To specify a port on another module use the PMx prefix. If the character X is used in place of x, the default side (1|2) is used.

For example:

sourcepic/port=pm2core2 cbfile _cb MBT1X 1 0 /flags=(IPORT=PM1TBANK2)

causes CORE2 on the 2nd processor module to get its data from TunerBank1 on the 1st processor module instead of the default source Module2.

OPORT=port - This specifies a non-default output routing for a CORE or TUNER port.

This specifies a non-default output routing for a CORE or TUNER port. the output for a CORE or TUNER is the HOST for acquisitions or the I/O module on the same side of the card for playback. This flag can be used to specify an alternate output port. Here are the available routing options for output ports:

Module    OPORT=HOST|NONE
Tuner     OPORT=HOST|NONE|THRUCOREx
Core      OPORT=HOST|NONE

where x is the port index, and the first entry in the list is the default.

If you are not routing to the default port, set the OPORT=NONE and use IPORT on the destination port to make the connection.

If the character X is used in place of x, the default side (1|2) is used.

For example:

sourcepic/port=tbank3 nafile _na MBT1X dec freq /flags=(OPORT=THRUCORE1)
picd set ^device CORE 0x1 /port=core1	   ! this enables the default noop core

causes TBANK3 to route its output through CORE1 before going to the host.

DELAYPORT=port - Select which ports 1=oddTuners 2=evenTuners or 3=allTuners (fed by port1) to

Select which ports 1=oddTuners 2=evenTuners or 3=allTuners (fed by port1) to place the delay line function (PPC=DLT) in front of. The delay is set in samples by setting the DELAY key. See HELP on keys.

Triggering

SGO - Slave acq/playback start to opposite channel acting as master

Slave acq/playback start to opposite channel acting as master

When synchronizing multiple ports on the slave side, use SGO for the first one, and RGO for the rest.

Output modules have a 5 deep output pipeline. This means that there will be 5 dead cycles between master going high and the 1st output sample. Digital output clocks will not start until the pipeline is ready, so the 1st output clock will be for the 1st output sample. With analog output, like the D2A, where there is no output clock to reference, the user must compensate for the 5 cycle delay if important. If an output module is used to trigger an input module, or an input to trigger an output, this delay must also be considered.

RGO - Ready acq/playback to start with channel on the same side.

Ready acq/playback to start with channel on the same side. (i.e. slave start of tuner1 with module1)

When synchronizing multiple ports on the slave side, use SGO for the first one, and RGO for the rest.

TGO - Use bit0 (or ext SMB if XGO and TGO) to trigger start.

Use bit0 (or ext SMB if XGO and TGO) to trigger start. this signal should be coincident with the data clock rising edge of the first sample of interest. If XSOE is enabled, the output signal will go high on the rising edge of the 2nd sample. To slave another channel or card to this signal, make sure to add both SGO and TGO to tell the slave that the enable signal is one sample late.

GGO - Use bit1 (or ext SMB if XGO and GGO) to gate the input clock.

Use bit1 (or ext SMB if XGO and GGO) to gate the input clock. is clocked in with the other input samples. Data is only processed when this bit is sampled high.

XGO - Applied with TGO, GGO, or SGO to use external sync SMB.

Applied with TGO, GGO, or SGO to use external sync SMB. The default sync sources are listed above.

XTGO - Shorthand for applying XGO and TGO.

Shorthand for applying XGO and TGO.

XSTGO - Shorthand for applying XGO, SGO and TGO.

Shorthand for applying XGO, SGO and TGO.

MTGO - Use the Module's external sync SMB to trigger start.

Use the Module's external sync SMB to trigger start.

XSOE - Enable external sync SMB output.

Enable external sync SMB output. This is high when port transfer is active.

Make sure this flag is the same for all ports on the same card. The setting for the last port enabled will over-ride all others. Note that this pin shows the port enable signal for Module-A only.

When acquiring, this signal goes high on the rising edge of the first sample clocked into the acquisition buffer. On playback, this signal is 3 clocks early due to output pipeline delays. When using TGO on acquisitions, this signal is delayed one sample to allow resynchronization for other slave channels.

XSTRM - Enable external sync 50ohm termination (on PIC8+).

Enable external sync 50ohm termination (on PIC8+).

XSTP - Use the internal test port on the PIC5 to implement the XGO trigger

Use the internal test port on the PIC5 to implement the XGO trigger instead of the SMB on the card edge. Usually combined as XTGO|XSTP.

Make sure this flag is the same for all ports on the same card. The setting for the last port enabled will over-ride all others. Note that this pin shows the port enable signal for Module-A only.

Filters

CFIR=name - Load the named file into the tuner Coarse (post CIC or CIC correction) Filter.

Load the named file into the tuner Coarse (post CIC or CIC correction) Filter. This is normally a halfband filter used to correct for the CIC droop. See pic_loadfc().

RFIR=name - Load the named file into the tuner Resampler Filter.

Load the named file into the tuner Resampler Filter. In FPGA implementations, this sits between the CFIR and PFIR filters. In Graychip implementations, this is after the PFIR.

PFIR=name - Load the named file into the tuner Programmable (post CFIR or final output) Filter.

Load the named file into the tuner Programmable (post CFIR or final output) Filter. This is normally a halfband filter used to shape the output response. See pic_loadfc().

FFIR=name - Load the named file into the special Filter Only Core.

Load the named file into the special Filter Only Core. See help on the FIRONLY flag for gain settings. See help on SOC with HHF for filter details.

LUT=name - Load the file named "lut_^name" into the post-tuner LUT-based demod.

Load the file named "lut_^name" into the post-tuner LUT-based demod. These are Midas files located in the dat directory of the ICE tree. They are generated by the ICEUTIL primitive. When used on a tuner port, the tuner is put in complex output mode. When used on a core port, the input must be complex (MBITS=-16). If the output is specified as complex, the real component contains the interpolated LUT output, and the imaginary contains the rough amplitude. This may be used for applying gain control.

Tuners

CHNS=n - Specify the number of configured tuner channels.

Specify the number of configured tuner channels. Default PIC2/PIC3 = 2, for MBT2/MBT3 = 24, for slimPIC = 4, PIC4 = 8.

CPC=n - Specify the number of channels per tuner chip.

Specify the number of channels per tuner chip. number of channels per chip reduces chip resources, and in some cases relaxes the minimum decimation limit for each channel.

Default PIC2/PIC3 = 1, for MBT2/MBT3/slimPIC/PIC4 = 4.

The MBT2/MBT3 with (CPC=4,minDec=32), (CPC=2,mindec=16), and (CPC=1,mindec=16)

The PIC4T/MBT4 with (CPC=4,mindec=16), (CPC=2,mindec=8), and (CPC=1,mindec=4)

Here is the available channel mapping for allowable values of CPC.

CPC=4    1,2,3,4,5,6,7,8, 9,10,11,12,13,14,15,16,  ...  25,26,27,28,29,30,31,32
CPC=2    1,2,    5,6,     9,10,      13,14,        ...  25,26,      29,30      
CPC=1    1,2,             9,10,                    ...  25,26

There is an alternate mapping for CPC=2 that is more natural on PIC4s

CPC=2    1,2,3,4,         9,10,11,12,              ...  25,26,27,28

The Odd numbered channels get data from the same input (default=Module1) The Even numbered channels get data from the same input (default=Module2)

FIRONLY - Bypasses the front end of the FPGA based tuners (PIC5+).

Bypasses the front end of the FPGA based tuners (PIC5+). filter elements are used to implement a full rate 63|127 tap filter at 64|32MHz.

If the special Filter Only core is loaded (SoC signature SSF or HHF) this flag will allow the KEY_GAIN settings in sourcepic to compensate for attenuation in the filter taps. If the filter is loaded with the FFIR=name flag, compensation for the known filter attenuation/gain is added to this value. If the filter is loaded through a separate LOADFC command, the gain setting must include the compensation for the filter attenuation/gain.

UFILT - Use the user defined programmable (PFIR) filter in tuner chips.

Use the user defined programmable (PFIR) filter in tuner chips. Without this flag, pic_reset will reload the default filters into the chips. This flag is automatically applied when the PFIR=name flag is present.

UCFIR - Use the user defined coarse (CFIR) filter in tuner chips.

Use the user defined coarse (CFIR) filter in tuner chips. Without this flag, pic_reset will reload the default filters into the chips. This flag is automatically applied when the CFIR=name flag is present.

URFIR - Use the user defined resampler (RFIR) filter in tuner chips on PIC5 boards.

Use the user defined resampler (RFIR) filter in tuner chips on PIC5 boards. Without this flag, pic_reset will reload the default filters into the chips. This flag is automatically applied when the RFIR=name flag is present.

NCFIR - Use the narrow-band CFIR coefficients on Graychips.

Use the narrow-band CFIR coefficients on Graychips.

PFIR4 - Decimate by 4 instead of 2 in PFIR stage on Graychips.

Decimate by 4 instead of 2 in PFIR stage on Graychips.

OVSR=N - Set the tuner oversampling factor to N.

Set the tuner oversampling factor to N.

AOVSR - Automatically apply oversampling ratio to allow lower tuner decimation.

Automatically apply oversampling ratio to allow lower tuner decimation. This switch must be applied to all tuners on the same side of the card. Each tuner must auto apply the same oversampling rate, which usually means they must have the same decimation.

Note: This flag is not stored on the card as the current OVSR value is. It must be applied to the handle (or primitive) that is actively changing the rate or decimation parameters. This is usually a SOURCEPIC.

If using multiple tuners with different decimations, this flag should be applied to the widest band tuner only. After a decimation/rate change is made to the wideband tuner, the other tuners will need to reset their decimation to pick up the OVSR change made by the wideband tuner.

POVSR - Use Post OVSR input rate as the basis for decimation and frequency parameters.

Use Post OVSR input rate as the basis for decimation and frequency parameters.

Normally, the libraries use the OVSR factor to relax the lower decimation limit of the chip but keep the user interface in terms of the Pre-OVSR input. The libraries internally adjust the actual tuned frequency, decimation, and gain used by the tuner chip.

If the post-OVSR rate is used as the defined input rate to the tuner, the integer decimation values supported by the tuner chips can effect a fractional decimation with respect to the pre-OVSR sample rate. When applying the POVSR flag, the SOURCEPIC primitive or PIC_IOPORT and other library calls should be told the Post-OVSR sample rate and treat it like a normal tuner operating on the oversampled input signal. The gain adjustment is still handled internally, but rates and frequencies are with respect to the oversampled input.

DSYNC - Turn off tuner NCO dither function

Force tuner NCO dither sync to affect turning off the NCO dither function. This is sometimes useful when making precision measurements.

FSYNC - Synchronize tuner frequency changes

Force tuner frequency changes to occur synchronously in multiple channels. Tuner 1 trigger the changes. Freq changes in channels 2-N will wait for the channel 1 change.

TALT1 - All tuners on INP=1 to make a SLIC3 act like half of a PIC4T

Make SLIC3 tuners behave as ports 1,3,5,7 all on module=1 port. This allows some applications written for a PIC4T to run on a laptop without alteration.

ITDEC - Allow independent tuner decimation for each channel on a GC4016.

Allow independent tuner decimation for each channel on a GC4016. This is only appropriate for CPC=2 and CPC=4 configurations. Do NOT use with CPC=1. Currently the ITDEC mode reduces the tuner output dynamic range from 96 to 84 dB. The lower 4 bits of each data word contain the channel number. This also requires sharc CPU cycles to demux the packets on PIC4/MBT4 cards.

ITFMT - Allow independent tuner format (SI|CI) for each channel on a GC4016 chip.

Allow independent tuner format (SI|CI) for each channel on a GC4016 chip. If combined with ITCPC, the format is only independent for each tuner chip.

ITCPC - Allow independent tuner Channels Per Chip (CPC=1|2|4) for each chip on a DTDM or DTDMX.

Allow independent tuner Channels Per Chip (CPC=1|2|4) for each chip on a DTDM or DTDMX. This adds the restriction that the format is the same for each channel on the same chip.

RESAMP - Enables digital resampling in the tuner.

Enables digital resampling in the tuner. and later cards supporting tuners. The resampling filter must be loaded using the LOADFC function and the resampling rate must be set by /RATIO=x switch on Midas primitives or the setKey(KEY_RATIO) in user code. The FPGA resampler in the PIC5 tuner has a default filter that should work well for most applications.

PRESAMP - Enables digital resampling in a tuner core placed in front of this resource.

Enables digital resampling in a tuner core placed in front of this resource. flag automatically allocates the FPGA tuner core on the same side of the card to resample the data before feeding the specified resource (usually a processor module core or tuner). See help on the RESAMP flag for more info.

NOTE: Current timecode accounting methods require all resources on the same side of the card to be started simultaneously when using the presampler. The RGO flag and master/slave SOURCEPIC mechanisms can be employed to accomplish this. The user cannot start and stop tuners or change their decimation while other channels on the same side are in use.

PRETUNE - Normalized frequency for presampler.

Normalized frequency for presampler.

PREGAIN - Gain for presampler tuner.

Gain for presampler tuner.

PRER2C - Enables digital Real to Complex conversion in the R2C core placed in front of this resource.

Enables digital Real to Complex conversion in the R2C core placed in front of this resource. This flag automatically allocates the FPGA R2C core on the same side of the processor module to convert a real signal to a complex signal at half the rate before feeding the MultiCore (usually a bank of tuners or an FFT channelizer) to increase the supported input bandwith.

NOTE: The FPGA load must have the R2C core in CORE1 and CORE2 for this to work.

NORESMON - Disable the PIC5 tuner resampler M over N circuit in favor of a straight

Disable the PIC5 tuner resampler M over N circuit in favor of a straight 28 bit accumulator.

TCLK=n - Sets the internal clock frequency for the Graychips on DTDM/DTDMX modules.

Sets the internal clock frequency for the Graychips on DTDM/DTDMX modules. to 101MHz to handle oversampling up to 100MHz. In some applications this can be increased to handle rates up to 110MHz if adequate cooling is supplied. TCLK=n is specified in Hz. For example config: ICEPIC,DEVNO=0,TCLK=110000000,IOM=A2D,...

PMWBT - Use WideBandTuner mode on Processor Modules.

Use WideBandTuner mode on Processor Modules. This loads an FPGA file with the same tuner resource parameters as the main board tuners but less resampler resources.

PMWBTR - Use WideBandTuner with WideBandResampler mode on Processor Modules.

Use WideBandTuner with WideBandResampler mode on Processor Modules. This loads an FPGA file with the same tuner and resampler resource parameters as the main board tuners.

FTTM=n - Fast Tuner Transform Mode controls various bank of tuners algorithms.

Fast Tuner Transform Mode controls various bank of tuners algorithms.

FTTM<0 Auto detect FTTM mode
FTTM=0 Shared dma channel, same decimation, FFT based channelizer (1024 chan/side)
FTTM=1 Shared dma channel, same decimation, set freq spacing, single pass (16 chan/side)
FTTM=2 Shared dma channel, same decimation, set freq spacing, two passes, A/B locked, (128 chan/side)
FTTM=3 Shared dma channel, same decimation, set freq spacing, three passes, A/B locked, (2048 chan/side)

By default, the tuners have FTTM turned off. With FTTM=0 an FFT based approach is used requiring a special PMFPGA=bt flag to load the FPGA. With FTTM>1 on a processor module, the FTT algorithm allows the tuner chips/cores to produce more channels than the FTTM=1 straight through approach. The algorithm uses half of the chips/cores to select blocks of the spectrum from the wideband input and write them to memory. The other chips/cores are used to further process these streams into individual channels.

FTTM==1

The tuners are run single pass with independent frequency, gain, and filters. The outputs are collected in memory until a packet length of data is available for each channel. The data for one packet for each channel are streamed in sequence through a single DMA channel. The host code then seperates each packet to an individual channel stream or a single stream with packet headers denoting the channel number for each packet.

FTTM>1

The algorithm with FTTM>1 will attempt to determine the following operational parameters on its own, but you can override these by specifying the following flags:

FTTD1=n Initial up front decimation
FTTN1=n Initial up front channels
FTTD2=n Stage 2 decimation
FTTN2=n Stage 2 channels
FTTD3=n Stage 3 decimation
FTTN3=n Stage 3 channels

The resampler can only be used if the ratio can be expressed as (P/X)*D2 where both P and X are a multiple of 64 bytes. X is the transfer length into the stage 2 tuners <= 512K. P is the stage 2 tuner production length <= 64K. The graychips do not support setting the resampler phase, so it must start and end each pass at phase=0.

FTTX2=n Stage 2 transfer length
FTTP2=n Stage 2 produce length

The front end tuner gains are set by the standard gain parameter. To set the gain in the 2nd and 3rd stage, use:

FTTG2=n Stage 2+ gain 

The number of usable channels depends on the FTTM mode, decimation, and channel spacing. The CHNS=n flag can be used to limit the number of channels output to less than the default of N1*N2*N3.

There are a number of restrictions. Apply the VERBOSE flag to see the actual parameters used. Resampling is applied to the last stage only.

FTTM==0

With FTTM=0, an FFT approach is used to affect a similar output. The complex input data is run through two polyphase FFTs with a cell width of twice the channel spacing and offset by one channel. The output of each cell in time is then processed through a resampler filter with a nominal bandwidth of 1/2 of the cell frequency (the channel spacing). The resample ratio must be between 1 and 4. The input sample rate must be chosen such that Fs is equal to the channel spacing times the FFT size which must be a power of 2 between 64 and 2048.

RF Parameters

RFFREQ=freq - Apply RF frequency in MHz

Apply RF frequency in MHz

RFBW=freq - Apply RF bandwidth in MHz

Apply RF bandwidth in MHz

RFATTN=db - Apply RF attenuation in dB

Apply RF attenuation in dB

RFGAIN=db - Apply RF gain in dB

Apply RF gain in dB

RFOPTS=(list) - Specify list of options as RFOPTS=(A|B|C) where current list includes:

Specify list of options as RFOPTS=(A|B|C) where current list includes:

ENABLE - enable options mask
XREF   - use eXternal reference
XADCLK - use eXternal A2D clock
ATTEN  - enable Attenuation
LNA    - enable Low Noise Amplifier
DCS    - enable DC Suppression
AIS    - enable Automatic Image Suppression
AGC    - enable Automatic Gain Control
BBAMP  - enable Base Band Amplifier

A2DOPTS=(list) - These are currently only parsed for the A2DM14 through A2DM18 modules.

These are currently only parsed for the A2DM14 through A2DM18 modules. Specify list of options as A2DOPTS=(A|B|C) where current list includes:

ENABLE - enable options mask
XREF   - use eXternal reference
XADCLK - use eXternal A2D clock
ATTEN  - enable Attenuation
LNA    - enable Low Noise Amplifier
DCS    - enable DC Suppression
AIS    - enable Automatic Image Suppression
AGC    - enable Automatic Gain Control

DCSBN=n - Order of exponential averaging in DCS algorithm.

Order of exponential averaging in DCS algorithm.

High Speed

HS - Use HighSpeed DMA link port mode (automatic for module/tuner ports).

Use HighSpeed DMA link port mode (automatic for module/tuner ports).

DUAL - Use two link ports per module (automatic when xfer rate > 38Mby/sec).

Use two link ports per module (automatic when xfer rate > 38Mby/sec). Sometimes necessary for IOC algorithms that put channel headers in one link port and data in the other.

QDRX=port - Uses both byte lanes per IO module to transfer data at 2x the rate.

Uses both byte lanes per IO module to transfer data at 2x the rate. This only works on PIC7 and later cards with certain high bandwidth IO modules that support it.

Port=1, 2, or 3 for both ports.

VHS - Use SHARC link ports in 48 bit mode for maximum transfer rates.

Use SHARC link ports in 48 bit mode for maximum transfer rates. On series-3 cards, theoretical xfer for non-VHS=80Mby/s VHS=120Mby/s. On series-4 cards, theoretical xfer for non-VHS=160Mby/s VHS=240Mby/s. If specified transfer rate needs more resources than one side, it will use resources from both sides requiring a MUXCLK=s flag. This requires the host side buffer size to be a multiple of 6 bytes.

Series-5 cards do not have SHARC link ports. The VHS flag is used to place the hypertransport links in double rate mode. Currently, the theoretical xfer rate per module for non-VHS=260Mby/s and VHS=520Mby/s. Both modules must operate in the same mode and VHS is automatically applied if one of the modules may need it. Use the VHS=0 flag to override this.

MEM=ALL - Specify card circular buffer memory to use ALL available.

Specify card circular buffer memory to use ALL available.

MEM=EXT - Specify card circular buffer memory to use extended memory.

Specify card circular buffer memory to use extended memory. On PIC4/MBT4 = (256kby), else not available.

CSIZE=n - Specify card circular buffer memory in 1K byte blocks.

Specify card circular buffer memory in 1K byte blocks. For default buffer sizes see HELP MEM. Buffer sizes can be from 2 to 128 Kbytes.

COFFS=n - Specify card circular buffer memory offset in 1K byte blocks.

Specify card circular buffer memory offset in 1K byte blocks. For default buffer offsets see HELP MEM Buffer offsets can be from 0 to 128-2 Kbytes.

FRAMEDELAY - Delays output of frame decimated output by one frame.

Delays output of frame decimated output by one frame. operating two synchronous channels framed at the same size and decimation so they don't hit the processor at the same time.

A2DPORTS=n - Number of active ports on an A2Dm18 dual site module:

Number of active ports on an A2Dm18 dual site module:

1 - just the A port (750Mby/s)
2 - independent A and B ports (750Mby/s each)
3 - just the A port using alternating AB resources (1500Mby/s)

Debug

VERBOSE - Print commands/status to screen (for debugging)

Print commands/status to screen (for debugging)

NOLOCK - Bypass multi-user locking mechanism (for debugging)

Bypass multi-user locking mechanism (for debugging)

PKTBLK=n - Sets blocking factor for output to emulate 10G switch fabric behavior.

Sets blocking factor for output to emulate 10G switch fabric behavior. Valid modes for N: 6=16K, 5=8K, 4=4K, 3=2K, 2=1K, 1=512, 0=256 samples.

NOCLKM - Over-ride automatic muxclk router.

Over-ride automatic muxclk router.

TO=n - Timeout value in seconds for DMA_WAIT function.

Timeout value in seconds for DMA_WAIT function. Defaults to -1 or an infinite blocking wait. A timeout of zero is a non-blocking WAIT, or returns -1 if not finished yet. Note: Current maximum wait value is 127 seconds and includes the duration of the transfer.

TP=n - Test Port number.

Test Port number.

N = 0  Base card FPGA
1  IO Module 1
2  IO Module 2
4  Base card EEPROM
7  Processor Module 1
8  Processor Module 2

TPOE=n - Enable Test Port output on 5+ series cards.

Enable Test Port output on 5+ series cards. This enables the output drivers on the 8-bit test port. This flag is only parsed during a hard reset. It can also be turned using setkey of TPOE during operation. On ICEPODs this port is the front LED display.

The test port number selects the internal function:

-1 - Status register set by write of KEY_TPD
0 - Off (enable silon if POD)
1 - Auxiliary core (default if no =n is specified) (GO trigger on bit0)
2 - PCI bus core
3 - I/O Module 1  
4 - I/O Module 2
5 - FPGA Core 1
6 - FPGA Core 2
7 - Processor Module 1
8 - Processor Module 2

If I/O Module 1 or 2 are selected, bit-0 of this port will mirror the XSYNC port enable signal and can be used for internal card-to-card triggering by specifying TPOE on the master card and the XTGO|XSTP flags on the slave card. This is useful if the external SMB on the slave card is needed for other purposes.

The display status register can be written and read by the test port data key KEY_TPD. This can be used to set the status leds on an ICEPOD device if TPOE=-1.

PMTPOE=n - Enable Test Port output on processor modules.

Enable Test Port output on processor modules.

0 - Off 
1 - DMA Controller
2 - Processor
3 - Hyper-Transport In
4 - Hyper-Transport Out
5 - Core 1
6 - Core 2
7 - Multi-Core 1
8 - Multi-Core 2

B32 - Only use lower 32 bits of PCI bus (ES45 hot-swap PCI workaround)

Only use lower 32 bits of PCI bus (ES45 hot-swap PCI workaround)

FORCE - Force reload of all programmable devices

During reset, a modules FPGA is only loaded if its current signature does not match the desired load. This option forces the download regardless of signature match.

MODDEBUG=n - Puts IO Module in Debug mode

On SDDS Modules, this leaves the clock running at 133Mby so the acquisition buffer can be used to analyze packet timing.

Config

NODE=address - Specifies the node name this device is plugged in to.

Specifies the node name this device is plugged in to. call will error if not run from this node. This allows a single config file to be shared by multiple nodes without inventing node specific device names. The combination of node name (NODE=name) and device number (DEVNO=n) uniquely define each card in the system.

SIDE=index - Select a specific side=1 or side=2 of the card.

Select a specific side=1 or side=2 of the card. This can be used to reset all odd or all even channels on a card. Apply this flag during a call to PIC_RESET(). From Midas use PICD/flags=side=N RESET <card>.

IOC=sig - Specify name of IO Controller file to load during a reset.

Specify name of IO Controller file to load during a reset. Filename is ice<card>_<sig> where card is pic4, mbt4, etc. Defaults are II, IIX, IO, OI, OO, etc... See HELP on IOC for complete list of supported downloads.

IOM=iomt_name - Specifies the type of IO modules on this card by name.

Specifies the type of IO modules on this card by name. If both modules are not the same, use IOM1=name and IOM2=name.

IOMFPGA=sig - Specify name of an FPGA load file to program the IO module.

Specify name of an FPGA load file to program the IO module. The filename is ice<iomname>_<sig> where:

<iomname> is the IO module name - a2dr13, rfxd, flzrxdr1, etc.
<sig> is the user defined signature, the first four characters being unique

The 4 character signature embedded in the FPGA should be <sig[1:4]> If both modules are not the same, use IOM1FPGA=sig and IOM2FPGA=sig.

PM=pmt_name - Specifies the type of Processor modules on this card by name.

Specifies the type of Processor modules on this card by name. If both modules are not the same, use PM1=name and PM2=name.

PMI=pmindex - Specifies the index of the processor module on this card to use for tuner and core resources.

Specifies the index of the processor module on this card to use for tuner and core resources. Defaults to PMI=1 if PM1 is installed. Use PMI=0 to force using resources on the main board. If both processor modules are of the same type, PMI=3 will utilize both of them.

PMFPGA=sig - Specify name of an FPGA load file to program the processor module.

Specify name of an FPGA load file to program the processor module. The filename is ice<pmname>_<io><sig> where:

<pmname> is the processor module name - dtdm, zppm, or v5pm. 
<io> is the base card interface type - "ss" for PIC4X, "hh" for all others
<sig> is the user defined signature, the first two characters being unique

The 4 character signature embedded in the FPGA should be <io><sig[1:2]> If both modules are not the same, use PM1FPGA=sig and PM2FPGA=sig.

NOPM - Specify that there are no Processor Modules on this PIC4X card

Specify that there are no Processor Modules on this PIC4X card

BIDIR - Allows Bi-directional modules to be used as input or output without changing

Allows Bi-directional modules to be used as input or output without changing the configuration string. For example an SDDSXD does not have to be in the configuration string as DXSDDS to perform output.

PRC=sig - Specify name of PRoCessor load file to use, default is "def".

Specify name of PRoCessor load file to use, default is "def". Filename is ice<card>_<sig> where card is dtdm, fppm, or pldm. See HELP on PRC for complete list of supported downloads.

PPC=sig - Specify name of PowerPC load file to use on a Processor Module, default is "def"

Specify name of PowerPC load file to use on a Processor Module, default is "def" Filename is ice<card>ppc_<sig> where card is dtdm, fppm, or pldm. See HELP on PPC for complete list of supported downloads.

IOMWAIT=sec - Number of seconds to wait after module reload for configuration discovery.

Number of seconds to wait after module reload for configuration discovery. By default SDDS modules will wait 5 sec and print an explanation for the delay. If this flag is specified, the informational message will not be displayed.

NOLOG - Turn off automatic temperature logging except at card reset.

Turn off automatic temperature logging except at card reset.

GPSMODE=mode - Sets non-standard behavior of the GPS module.

Sets non-standard behavior of the GPS module.

mode=0 - enable 10MHz reference without GPS training or 1PPS output
mode=1 - enable 10MHz reference, GPS training, 1PPS output and IRIG-B (def)
mode=2 - enhanced mode for platforms in motion

The mode selection changes the defaults for the GPSOPTS flag. To set mode=0 and still put out a sloppy 1PPS use the combined flags: GPSMODE=0|GPSOPTS=(-NPPS).

It should be specified in the card definition alias if at all possible. Normally, the GPS module is not reset during a typical card reset or FORCE=1 reset. To change this flag value after the card is up and running, you must add the flag FORCE=2 and issue a reset.

GPSOPTS=(list) - Specify list of options as GPSOPTS=(A|B|C) where current list includes:

Specify list of options as GPSOPTS=(A|B|C) where current list includes:

NPPS - NoPPS turns off the 1PPS output
DPPS - Direct PPS from the GPS Reciever (no conditioning)
APWR - enable 5V antennae power
AFVP - enable fast response to reverse voltage protection
PTST - PPS test mode outputs the GPS's PPS on the IRIG-B port

It should be specified in the card definition alias if at all possible. This flag needs to be specified with the flag FORCE=2 if changing the value.

VRT=(list) - This flag configures the VRT transmit/receive core parameters.

This flag configures the VRT transmit/receive core parameters.

The list of parameters are specified using the form VRT=(KEY1=VALUE1,KEY2=VALUE2,...)

The valid keyed parameters are:

SIZE - the size of the data section in bytes (def=1440)
BITS - number of bits per sample 6|8|12|16 (def=MBITS)
OUID - the organizationally unique ID (def=ICE)
SID  - stream ID or channel number (def=0)
CID  - information:packet class IDs (def=ICE) 
TSIS - time stamp integer seconds  (def=0)
TSFS - time stamp fractional seconds (def=0.0)
TLR  - packet trailer (def=0) or =NONE to exclude from packet

FFT=(list) - This flag configures the FFT core parameters.

This flag configures the FFT core parameters.

The list of parameters are specified using the form VRT=(KEY1=VALUE1,KEY2=VALUE2,...)

The valid keyed parameters are:

NFFT - the size of the FFT 
NOUT - the size of the FFT output
NMAX - number of frames to block maximum
NAVG - number of frames to block average
NEXP - number of frames to exponentially average
FLAGS - options mask "INV|AC|MAG|EXP|MAX"
FPPF - name of 4*SIZE forward polyphase filter file
WIND - name of standard window file

CORE=(list) - This flag configures the generic CORE parameters.

This flag configures the generic CORE parameters.

The list of parameters are specified using the form CORE=(KEY1=VALUE1,KEY2=VALUE2,...)

The valid keyed parameters are:

DEC   - the decimation in the core 
FLAGS - the flags bitmask for the core

TimeCode

TC=mode - Set the timecode mode as described in the help on pic_tc.

Set the timecode mode as described in the help on pic_tc.

OKNC - Turn off clock loss detect circuit.

Turn off clock loss detect circuit.

This flag is useful in applications where the timecode NoClock error status is bogus or otherwise ignorable. This flag causes pic_tc() to replace the status with a TC_OKNC status. This flags the noClock problem but is still a positive value indicating an OK timecode value.

Examples: Using SINKPIC/throttle=2 to play back intermittently sets the sample rate to 10e3 triggering the noClock bit. But this is OK.

NOTE: The IOC has a clock loss circuit for input data rates > 200kHz. If no clocks are detected over a 5usec period, it is assumed that the clock, even if it recovers, may have had glitches that would render the timecode values invalid. If this occurs, PIC_TC will return a -7 status until the acquisition is restarted. The OKNC flag turns this status into a TC_OKNC status which recognizes the timecode as good, assuming the noClock is bogus.

NOTCFILL - Do Not require fill bits prior to barker in SDN and DTL modes.

Do Not require fill bits prior to barker in SDN and DTL modes. necessary for tape playback where fill bits may be replaced with status bits.

OPPSOFFSET=n - Number of clock cycles offset between the 1PPS signal capture and the data capture.

Number of clock cycles offset between the 1PPS signal capture and the data capture. A positive value means the 1PPS precedes the actual data it corresponds to by N samples.

An A2D, for instance, often has 4 data pipeline stages between its input and output, but typically the 1PPS signal is captured coincident with the A2Ds output register. The 1PPS, if captured with the LSBX flag, will show up in the data stream 4 samples earlier than the data it corresponds to.

This defaults to the value +4 for A2D modules, and 0 for all others. Some modules, like the FCXD or LVDS will need to set this when being driven by an A2D or some other source with pipeline delays relative to the 1PPS.

ATCCALIB=n - Additional timecode calibration in units of post tuner/core samples.

Additional timecode calibration in units of post tuner/core samples. to any internal calibration known to the ICE libraries. User supplied filters or cores may introduce group delays that are not calibrated by the standard ICE library. This flag allows SOURCEPIC to forward corrected timecode information without forcing the user to intercept and modify the possibly high rate packet data streams.

LEAPSECDOY=n - This tells the ICE libraries that there will be a mid-year leap second on DayOfYear=n.

This tells the ICE libraries that there will be a mid-year leap second on DayOfYear=n. UTC based timecode including the ICE packets will repeat a second and SDDS counters will not, a correction needs to be applied for the remainder of the year to all SDDS streams. This can be applied globally to all configurations by adding it to the file $ICEROOT/cfg/global_flags.cfg .

Note: While this method does not rely on the system clock for determining the year to apply this adjustment, or a reset at the leap second insertion, or at the roll over to the next year, it does require this file to be removed or modified before this day of the next year.

Note: DayOfYear is zero based as returned from the timex routine in Midas. So July-1-2012 DoY=182.

Note: LEAPSECDOY <= 0 will be ignored.

Network

IPVLAN=vlan - Specify the Default Virtual Local Area Network address for this UDP module.

Specify the Default Virtual Local Area Network address for this UDP module. This sets the VLAN for all ensuing IPADDRx, IPCONNx, or IPDISCx commands.

Example: IPVLANx=24,IPADDRx=192.9.200.100

Where x = 1|2 for the 1st or 2nd module. Both if x is not specified. Where vlan = is a legal VLAN number between 1 and 4095

NOTE: The IPVLAN flags must be applied during the card reset to force loading the VLAN support. The vlan value at reset is not important, so simply adding IPVLAN without the equals to the flags string is sufficient.

IPADDR=ip - Specify the IP address of this UDP module.

Specify the IP address of this UDP module. the module will respond to for ARP/ICMP messages. The HW address of the module is also constructed by pre-pending the value 00:60 to this IP address supplied.

Example: IPADDRx=192.9.200.100

Where x = 1|2 for the 1st or 2nd module. Both if x is not specified. Where ip = aaa.bbb.ccc.ddd in string notation

IPCONN=ip - Specify the IP address of for the UDP module to connect to.

Specify the IP address of for the UDP module to connect to. address (multicast address) from which to receive data. This Multicast address is a group that contains listeners. Within the module, router queries to listeners of this address will be automatically replied to until the module is told to "leave" the group.

Example: IPCONNx=192.9.200.101

Where x = 1|2 for the 1st or 2nd module. Both if x is not specified. Where ip = aaa.bbb.ccc.ddd in string notation

IPDISC=ip - Specify the IP address of for the UDP module to disconnect from.

Specify the IP address of for the UDP module to disconnect from. group address (multicast address) that you want to "leave".

Example: IPDISCx=192.9.200.101

Where x = 1|2 for the 1st or 2nd module. Both if x is not specified. Where ip = aaa.bbb.ccc.ddd in string notation

IPDEST=ip - Specify the IP address of for the UDP module to send to.

Specify the IP address of for the UDP module to send to. address (multicast address) on which to transmit data. This Multicast address is a group that contains listeners. Within the module, router queries to listeners of this address will be automatically replied to until the module is told to "leave" the group.

Example: IPDESTx=192.9.200.101 Example: IPDESTx=224.9.200.101:9001

Where x = 1|2 for the 1st or 2nd module. The x is required. Where ip = aaa.bbb.ccc.ddd[:port] in string notation, the port is optional

PREDELAY=N - This option throws away the first N milliseconds of SDDS data packets that are received after the JOIN.

This option throws away the first N milliseconds of SDDS data packets that are received after the JOIN. Many switches do not guarantee smooth delivery for the first 60 milliseconds. This eliminates most startup induced out-of-order or dropped packets. The maximum delay allowed is 255 milliseconds.

TGPORTS=n - Number of active Ten Gig Ethernet ports on a TGSXD dual site module:

Number of active Ten Gig Ethernet ports on a TGSXD dual site module:

0 - just the A port using alternating AB resources (1250Mby/s)
1 - just the A port (750Mby/s)
2 - independent A and B ports (750Mby/s each)
3 - raw high speed mode (1250Mby/s)

UOPT - User OPTion - In SDDS modes, leaves ICE/SDDS headers in stream and disables data reformatting

User OPTion - In SDDS modes, leaves ICE/SDDS headers in stream and disables data reformatting

Network Debug

RXICESDDS - The default SDDS mode (Native Mode) for proper tuner|module operation and timecode interpretation.

The default SDDS mode (Native Mode) for proper tuner|module operation and timecode interpretation.

The UDP module presents the ICE 8-byte sync.addr.port Header, SDDS Packet Header, and SDDS Data, to the IOC running IIS or IOS to strip off the header, interpret timecode, and unpack the data words for the proper tuner or module input.

In Native(ICE) mode, the UDP module filters Parity Packets and Non-Standard SDDS packets. Standard SDDS packets have the "Standard Format" bit set in the Format Identifier Field of the SDDS Header. By default, SDDS Packets without this bit set are filtered.

Parity and Non-Standard Packets may be acquired in Native mode, by using the flags RXALLOWPRYPKT and/or RXALLOWNSPKT, respectively.

Also by default, Native(ICE) mode uses a "strict" format where only 1 data source Multicast address is allowed to be acquired. All other Multicast data sources are filtered. The Multicast address that is acquired is always set to the last Multicast address that is joined. When using the strict mode, the user should be sure to "leave" a Multicast before joining another. Only the last joined Multicast address will be retained.

To turn "off" strict mode a user can use the flag RXSTRICTOFF. This will allow up to 4 Multicast sources to be acquired per module.

If the UOPT flag is included, the ICE and SDDS headers are not stripped off of the module data. They are always stripped off of the tuner input.

When RXRAWDATA, RXRAWSDDS, RXPKTSDDS, Or RXSDDSDATA are Not Present, RXICESDDS Is Assumed

RXRAWDATA - Bring In Every And All Packets Data/Headers.

Bring In Every And All Packets Data/Headers.

RXRAWBURST - Bring In All Packet wout/Tx Response.

Bring In All Packet wout/Tx Response.

RXRAWSDDS - Bring In Only SDDS Packet Header & Data, NO UDP,IP Hdrs.

Bring In Only SDDS Packet Header & Data, NO UDP,IP Hdrs.

RXSDDSDATA - Bring In Only SDDS Data, No Headers

Bring In Only SDDS Data, No Headers

RXPKTSDDS - Bring In Data With ICE (8 Byte) & SDDS Headers And SDDS Data Without Need For IIS or IOS Download

Bring In Data With ICE (8 Byte) & SDDS Headers And SDDS Data Without Need For IIS or IOS Download

RXALLOWPRYPKT - Allow Acquisition Of SDDS Parity Pkts.

Allow Acquisition Of SDDS Parity Pkts.

RXALLOWNSPKT - Allow Acquisition Of Non-Standard SDDS Pkts.

Allow Acquisition Of Non-Standard SDDS Pkts.

RXSTRICTOFF - Allow Multiple MC Joins.

Allow Multiple MC Joins.

RXNOSEQFILL - Do NOT insert filler for dropped SDDS packets based on sequence checks.

Do NOT insert filler for dropped SDDS packets based on sequence checks.

RXTCBSWAP - Swaps bits 0 and 3 in 16 bit SDDS packets to move TimeCodeBit=3 into selectable bit=0.

Swaps bits 0 and 3 in 16 bit SDDS packets to move TimeCodeBit=3 into selectable bit=0. NOTE: This is only needed on PIC4/MBT4 cards as PIC5s allow TC=SDN3

TXRAWDATA - Send Out Packets With 1080 Bytes Of Data, All From User, SDDS Hdr Not Generated

Send Out Packets With 1080 Bytes Of Data, All From User, SDDS Hdr Not Generated

TXRAWSDDS - Send Out Packets With SDDS Hdr (56 Bytes) Generated By Module, 1024 Bytes From User

Send Out Packets With SDDS Hdr (56 Bytes) Generated By Module, 1024 Bytes From User This is the default for output on an DXSDDS module.

TXVLANOVRIDE - Enable protected VLAN range used to insert a signal into the SDDS network.

Enable protected VLAN range used to insert a signal into the SDDS network. Disabled by default to prevent accidental SDDS loop problems.

SDDSLEAK=n - Leaks the SDDS packet data at the nominal rate to prevent tuner starvation at low

Leaks the SDDS packet data at the nominal rate to prevent tuner starvation at low data rates or from simulators that do not maintain true SDDS latency requirements. User must specify n = number of bits per sample in the SDDS Packet stream, and specify the correct data rate in the pic_ioport() call.

NOLINK - Disable link negotiation.

Disable link negotiation.

NetIO

NIO=type - Packet type for network IO (ICE,SDDS,VRT,VRTX)

Packet type for network IO (ICE,SDDS,VRT,VRTX)

NIOC=N - Number of channels in this DMA multichannel port

Number of channels in this DMA multichannel port Append the multichannel index to the NIOA, SID, and SR flags to set each index (#=1:N)

IPADDR - IP Address for one of the four SFP 10G ports on the QSFP (where #=1:4 SFP index)

IP Address for one of the four SFP 10G ports on the QSFP (where #=1:4 SFP index)

NIOA - Output IP or Multicast Address of this channel output (# is optional multichannel index)

Output IP or Multicast Address of this channel output (# is optional multichannel index) The syntax is: NIOAx=Q.S/a.b.c.d where Q=SFP index (1:4), S=slot (1:4 per SFP), and a.b.c.d is the network address)

SID - Stream ID for Vita49 packet mode (# is optional multichannel index)

Stream ID for Vita49 packet mode (# is optional multichannel index)

SR - Override computed Sample Rate in MHz (# is optional multichannel index)

Override computed Sample Rate in MHz (# is optional multichannel index)

SrvIce

CARD=N - config string for card N is inserted here

config string for card N is inserted here

PORT=port - port on card to use (ie MODULE1,TUNER2,TBANK21)

port on card to use (ie MODULE1,TUNER2,TBANK21)

RATE=rate - sample rate in Hertz

sample rate in Hertz

BITS=bits - sample size in bits

sample size in bits

LENGTH=len - length of circular memory buffer in seconds

length of circular memory buffer in seconds

DIR=io - direction of transfer (-1=input 1=output)

direction of transfer (-1=input 1=output)

XFER=len - transfer length in bytes

transfer length in bytes

FUNC=func - argument to pic_dmafunc (-2=continuous, >0=#passes)

argument to pic_dmafunc (-2=continuous, >0=#passes)

FILE=filename - filename to write into or read from

filename to write into or read from

Other

ADGAINFORCE - Turn off A2Dr13 overdrive tracking algorithm.

Turn off A2Dr13 overdrive tracking algorithm.

ADWARNOFF - Turn off warning when using ADGAINFORCE.

Turn off warning when using ADGAINFORCE.

ADGAINTRACK - Allow A2Dr13 gain to track signal up/down.

Allow A2Dr13 gain to track signal up/down.

ADDELAY - Have A2D consume the first 1M samples to cover the gain overdrive adjustment transient.

Have A2D consume the first 1M samples to cover the gain overdrive adjustment transient.

EMT - Sets the parameters for the Envelope Measure and Track function.

Sets the parameters for the Envelope Measure and Track function. This computes an 2**M length exponetial average of the N length block maximum of the magnitude of the high byte of the input samples. The parameters are packed as (M<<12)|N into a 16 bit register so the valid parameter ranges are (0<N<4096) and (0<M<16). The default is 0x4400, or M=4, N=1024.