VCORE

streams data through an FPGA Verilog Core Simulation

<IN>		 - Input File
<OUT>		 - Output File
<FUNC>		 - Function (FIR,TFDD,CIC,PCIE)
<P2>		 - Optional Parameter 2 
<P3>		 - Optional Parameter 3 
<P4>		 - Optional Parameter 4 

The Verilator project converts verilog code into executable C++ code
which is compiles into the VCore object in the ICE library area.
This primitive instantiates that class and runs data through it as
if it were in a PORT=CORE slot of an ICE DMA engine.

Examples:

Switches:
  /TL - Switch description
  /W - PCIE write TLP
  /R - PCIE read TLP
  /T - PCIE link training