I/O modules

The digital I/O module sites can be configured for four types of electrical interfaces: S) 16-bit single ended TTL, D) 16-bit LVDS, H) bidirectional 8-bit LVDS, or R) 4-lane bidirectional RocketIO. The connector accepts a ribbon cable connector or one of the 2×2.6in form factor modules listed below. The module sites use FPGAs to perform optional clock and MSB inversion, muxing/demuxing of data bits, packet parsing, and time code processing. The standard FPGA program supports 1, 4, 8, or 16 bit data words, real or complex. If an ICE-A2D or ICE-D2E is connected, the FPGA can also be used to generate a sampling clock if not supplied externally. Dual module sites are clocked independently to allow for short/long term clock skew or different sampling rates. They may also be locked to either one of the sources.

If you need to remove an I/O module on a ICE-PIC card please click here for instructions. For specific measurements for PIC5+ I/O modules please click here.